CONFIG_CLOCK_STM32_PLL_P_DIVISOR

PLL division factor for main system clock

PLL division factor for main system clock

PLL P Divisor

Type: int

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PLLP division factor needs to be set correctly to not exceed 120MHz. Allowed values: 2, 4, 6, 8

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PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8

Help

PLL P Output divisor, allowed values: 0, 7, 17.

Kconfig definitions

At boards/arm/disco_l475_iot1/Kconfig.defconfig:49

Included via Kconfig:10 → Kconfig.zephyr:19

Menu path: (top menu)

config CLOCK_STM32_PLL_P_DIVISOR
    int
    default 7 if CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1
    depends on CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1

At drivers/clock_control/Kconfig.stm32:218

Included via Kconfig:10 → Kconfig.zephyr:29 → drivers/Kconfig:54 → drivers/clock_control/Kconfig:45

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_P_DIVISOR
    int
    prompt "PLL division factor for main system clock" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 8 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 2 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLLP division factor needs to be set correctly to not exceed 120MHz.
      Allowed values: 2, 4, 6, 8

At drivers/clock_control/Kconfig.stm32:283

Included via Kconfig:10 → Kconfig.zephyr:29 → drivers/Kconfig:54 → drivers/clock_control/Kconfig:45

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_P_DIVISOR
    int
    prompt "PLL division factor for main system clock" if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 8 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 4 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLLP division factor needs to be set correctly to not exceed 84MHz.
      Allowed values: 2, 4, 6, 8

At drivers/clock_control/Kconfig.stm32:345

Included via Kconfig:10 → Kconfig.zephyr:29 → drivers/Kconfig:54 → drivers/clock_control/Kconfig:45

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_P_DIVISOR
    int
    prompt "PLL P Divisor" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 0 17 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 7 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL P Output divisor, allowed values: 0, 7, 17.

(Definitions include propagated dependencies, including from if’s and menus.)