Help¶

When selected the Page address extension mode is enabled. The PAE page tables provides a mechanism to selectively disable execution. So any Page Table Entry (PTE) that sets the XD bit will have all instruction fetches disabled in that 4KB region. The amount of RAM needed for PAE tables is more than twice that of 32-Bit paging because each PAE entry is 64bits wide. Note: Do not enable in RAM constrained devices.

Direct dependencies¶

X86_MMU && X86

(Includes any dependencies from if’s and menus.)

Defaults¶

No defaults. Implicitly defaults to n.

Symbols that select this symbol¶

SOC_ATOM

Kconfig definition¶

At arch/x86/Kconfig:83

Included via Kconfig:10 → Kconfig.zephyr:23 → arch/Kconfig:16

Menu path: (top menu) → X86 Architecture Options → Processor Capabilities → Memory Management

config X86_PAE_MODE
    bool
    prompt "Enable PAE page tables" if X86_MMU && X86
    depends on X86_MMU && X86
    help
      When selected the Page address extension mode is enabled. The PAE
      page tables provides a mechanism to selectively disable execution.
      So any Page Table Entry (PTE) that sets the XD bit will have all
      instruction fetches disabled in that 4KB region. The amount of RAM
      needed for PAE tables is more than twice that of 32-Bit paging
      because each PAE entry is 64bits wide.
      Note: Do not enable in RAM constrained devices.

(Definitions include propagated dependencies, including from if’s and menus.)