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Configuration Options

Overview

Kconfig files describe build-time configuration options (called symbols in Kconfig-speak), how they’re grouped into menus and sub-menus, and dependencies between them that determine what configurations are valid.

Kconfig files appear throughout the directory tree. For example, subsys/power/Kconfig defines power-related options.

This documentation is generated automatically from the Kconfig files by the genrest.py script. Click on symbols for more information.

Subsystems

These index pages list symbols defined within a particular subsystem, while the list below includes all configuration symbols.

All configuration options

Symbol name

Help/prompt

CONFIG_2ND_LEVEL_INTERRUPTS

Second level interrupts are used to increase the number of addressable interrupts in a system.

CONFIG_2ND_LVL_INTR_00_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_01_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_02_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_03_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_04_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_05_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_06_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_07_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_ISR_TBL_OFFSET

This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts.

CONFIG_3RD_LEVEL_INTERRUPTS

Third level interrupts are used to increase the number of addressable interrupts in a system.

CONFIG_3RD_LVL_INTR_00_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_01_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_02_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_03_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_04_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_05_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_06_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_07_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_ISR_TBL_OFFSET

This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts.

CONFIG_64BIT

This option tells the build system that the target system is using a 64-bit address space, meaning that pointer and long types are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it.

CONFIG_ACPI

Allow retrieval of platform configuration at runtime.

CONFIG_ADC

Enable ADC (Analog to Digital Converter) driver configuration.

CONFIG_ADC_0

Enable ADC 0

CONFIG_ADC_1

Enable ADC1

CONFIG_ADC_2

Enable ADC 2

CONFIG_ADC_ASYNC

This option enables the asynchronous API calls.

CONFIG_ADC_CONFIGURABLE_INPUTS

CONFIG_ADC_LOG_LEVEL

CONFIG_ADC_LOG_LEVEL_DBG

Debug

CONFIG_ADC_LOG_LEVEL_ERR

Error

CONFIG_ADC_LOG_LEVEL_INF

Info

CONFIG_ADC_LOG_LEVEL_OFF

Off

CONFIG_ADC_LOG_LEVEL_WRN

Warning

CONFIG_ADC_MCUX_ADC12

Enable the MCUX ADC12 driver.

CONFIG_ADC_MCUX_ADC16

Enable the MCUX ADC16 driver.

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_1

Divide ratio is 1

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_2

Divide ratio is 2

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_4

Divide ratio is 4

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_8

Divide ratio is 8

CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE

Alternate reference pair

CONFIG_ADC_MCUX_ADC16_VREF_DEFAULT

Default voltage reference pair V_REFH and V_REFL

CONFIG_ADC_NRFX_ADC

Enable support for nrfx ADC driver for nRF51 MCU series.

CONFIG_ADC_NRFX_ADC_CHANNEL_COUNT

Number of ADC channels to be supported by the driver. Each channel needs a dedicated structure in RAM that stores the ADC settings to be used when sampling this channel.

CONFIG_ADC_NRFX_SAADC

Enable support for nrfx SAADC driver for nRF52 MCU series.

CONFIG_ADC_SAM0

Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver.

CONFIG_ADC_SAM_AFEC

Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module.

CONFIG_ADC_SHELL

Enable ADC Shell for testing.

CONFIG_ADC_STM32

Enable the driver implementation for the stm32xx ADC

CONFIG_ADC_XEC

Enable ADC driver for Microchip XEC MCU series.

CONFIG_ADT7420

Enable the driver for Analog Devices ADT7420 High-Accuracy 16-bit Digital I2C Temperature Sensors.

CONFIG_ADT7420_TEMP_CRIT

The critical overtemperature pin asserts when the temperature exceeds this value. The default value of 147 is the reset default of the ADT7420.

CONFIG_ADT7420_TEMP_HYST

Specify the temperature hysteresis in °C for the THIGH, TLOW, and TCRIT temperature limits.

CONFIG_ADT7420_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADT7420_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADT7420_TRIGGER

CONFIG_ADT7420_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADT7420_TRIGGER_NONE

No trigger

CONFIG_ADT7420_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ADXL362

Enable driver for ADXL362 Three-Axis Digital Accelerometers.

CONFIG_ADXL362_ABS_REF_MODE

Unsigned value that sets the ADXL362 interrupt mode in either absolute or referenced mode. 0 - Absolute mode 1 - Referenced mode

CONFIG_ADXL362_ACCEL_ODR_100

100 Hz

CONFIG_ADXL362_ACCEL_ODR_12_5

12.5 Hz

CONFIG_ADXL362_ACCEL_ODR_200

200 Hz

CONFIG_ADXL362_ACCEL_ODR_25

25 Hz

CONFIG_ADXL362_ACCEL_ODR_400

400 Hz

CONFIG_ADXL362_ACCEL_ODR_50

50 Hz

CONFIG_ADXL362_ACCEL_ODR_RUNTIME

Set at runtime.

CONFIG_ADXL362_ACCEL_RANGE_2G

2G

CONFIG_ADXL362_ACCEL_RANGE_4G

4G

CONFIG_ADXL362_ACCEL_RANGE_8G

8G

CONFIG_ADXL362_ACCEL_RANGE_RUNTIME

Set at runtime.

CONFIG_ADXL362_ACTIVITY_THRESHOLD

Unsigned value that the adxl362 samples are compared to in activity trigger mode.

CONFIG_ADXL362_INACTIVITY_THRESHOLD

Unsigned value that the adxl362 samples are compared to in inactivity trigger mode.

CONFIG_ADXL362_INTERRUPT_MODE

Unsigned value that sets the ADXL362 in different interrupt modes. 0 - Default mode 1 - Linked mode 3 - Loop mode

CONFIG_ADXL362_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADXL362_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADXL362_TRIGGER

CONFIG_ADXL362_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADXL362_TRIGGER_NONE

No trigger

CONFIG_ADXL362_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ADXL372

Enable driver for ADXL372 Three-Axis Digital Accelerometers.

CONFIG_ADXL372_ACTIVITY_THRESHOLD

Threshold for activity detection.

CONFIG_ADXL372_ACTIVITY_TIME

The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below.

CONFIG_ADXL372_BW_1600HZ

1600 Hz

CONFIG_ADXL372_BW_200HZ

200 Hz

CONFIG_ADXL372_BW_3200HZ

3200 Hz

CONFIG_ADXL372_BW_400HZ

400 Hz

CONFIG_ADXL372_BW_800HZ

800 Hz

CONFIG_ADXL372_HPF_CORNER0

ODR/210

CONFIG_ADXL372_HPF_CORNER1

ODR/411

CONFIG_ADXL372_HPF_CORNER2

ODR/812

CONFIG_ADXL372_HPF_CORNER3

ODR/1616

CONFIG_ADXL372_HPF_DISABLE

Disabled

CONFIG_ADXL372_I2C

I2C Interface

CONFIG_ADXL372_INACTIVITY_THRESHOLD

Threshold for in-activity detection.

CONFIG_ADXL372_INACTIVITY_TIME

The time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR.

CONFIG_ADXL372_LPF_DISABLE

Disabled

CONFIG_ADXL372_MEASUREMENT_MODE

In this mode, acceleration data is provided continuously at the output data rate (ODR).

CONFIG_ADXL372_ODR_1600HZ

1600 Hz

CONFIG_ADXL372_ODR_3200HZ

3200 Hz

CONFIG_ADXL372_ODR_400HZ

400 Hz

CONFIG_ADXL372_ODR_6400HZ

6400 Hz

CONFIG_ADXL372_ODR_800HZ

800 Hz

CONFIG_ADXL372_PEAK_DETECT_MODE

In most high-g applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. In this mode the device returns only the over threshold Peak Acceleration between two consecutive sample fetches.

CONFIG_ADXL372_REFERENCED_ACTIVITY_DETECTION_MODE

Activity detection can be configured as referenced or absolute. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation.

CONFIG_ADXL372_SPI

SPI Interface

CONFIG_ADXL372_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADXL372_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADXL372_TRIGGER

CONFIG_ADXL372_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADXL372_TRIGGER_NONE

No trigger

CONFIG_ADXL372_TRIGGER_OWN_THREAD

Use own thread

CONFIG_AHB_DIV

AHB clock divider

CONFIG_AK8975

Enable driver for AK8975 magnetometer.

CONFIG_AK8975_I2C_ADDR

I2C address of the AK8975 sensor. Choose:

  • 0x0C if CAD1 connected to GND and CAD0 is connected to GND

  • 0x0D if CAD1 connected to GND and CAD0 is connected to VDD

  • 0x0E if CAD1 connected to VDD and CAD0 is connected to GND

  • 0x0F if CAD1 connected to VDD and CAD0 is connected to VDD

If the AK8975 sensor is part of a MPU9159 chip, the I2C address needs to be 0x0C.

CONFIG_AK8975_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which the AK8975 chip is connected.

CONFIG_AK8975_NAME

Device name with which the AK8975 sensor is identified.

CONFIG_ALTERA_AVALON_I2C

CONFIG_ALTERA_AVALON_MSGDMA

CONFIG_ALTERA_AVALON_QSPI

CONFIG_ALTERA_AVALON_SYSID

CONFIG_ALTERA_AVALON_TIMER

This module implements a kernel device driver for the Altera Avalon Interval Timer as described in the Embedded IP documentation, for use with Nios II and possibly other Altera soft CPUs. It provides the standard “system clock driver” interfaces.

CONFIG_AMG88XX

Enable driver for AMG88XX infrared thermopile sensor.

CONFIG_AMG88XX_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_AMG88XX_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_AMG88XX_TRIGGER

CONFIG_AMG88XX_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_AMG88XX_TRIGGER_NONE

No trigger

CONFIG_AMG88XX_TRIGGER_OWN_THREAD

Use own thread

CONFIG_AMS_IAQ_CORE

Enable driver for iAQ-core Digital VOC sensor.

CONFIG_APA102_STRIP

Enable the LED strip driver for a chain of APA102 RGB LEDs. These are sold as DotStar by Adafruit and Superled by others.

CONFIG_APDS9960

Enable driver for APDS9960 sensors.

CONFIG_APDS9960_AGAIN_16X

16x

CONFIG_APDS9960_AGAIN_1X

1x

CONFIG_APDS9960_AGAIN_4X

4x

CONFIG_APDS9960_AGAIN_64X

64x

CONFIG_APDS9960_ENABLE_ALS

Enable Ambient Light Sense (ALS).

CONFIG_APDS9960_PGAIN_1X

1x

CONFIG_APDS9960_PGAIN_2X

2x

CONFIG_APDS9960_PGAIN_4X

4x

CONFIG_APDS9960_PGAIN_8X

8x

CONFIG_APDS9960_PLED_BOOST_100PCT

100%

CONFIG_APDS9960_PLED_BOOST_150PCT

150%

CONFIG_APDS9960_PLED_BOOST_200PCT

200%

CONFIG_APDS9960_PLED_BOOST_300PCT

300%

CONFIG_APDS9960_PPULSE_COUNT

Proximity Pulse Count

CONFIG_APDS9960_PPULSE_LENGTH_16US

16us

CONFIG_APDS9960_PPULSE_LENGTH_32US

32us

CONFIG_APDS9960_PPULSE_LENGTH_4US

4us

CONFIG_APDS9960_PPULSE_LENGTH_8US

8us

CONFIG_APDS9960_TRIGGER

CONFIG_APDS9960_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_APDS9960_TRIGGER_NONE

No trigger

CONFIG_APIC_TIMER

Use the “new” local APIC timer driver for the system timer. This is a replacement for the legacy local APIC timer driver which supports tickless operation, but not the Quark MVIC.

CONFIG_APIC_TIMER_IRQ

This option specifies the IRQ used by the local APIC timer.

CONFIG_APIC_TIMER_IRQ_PRIORITY

This option specifies the IRQ priority used by the local APIC timer.

CONFIG_APIC_TIMER_TSC

If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32().

CONFIG_APIC_TIMER_TSC_M

TSC to local APIC timer frequency divisor (M)

CONFIG_APIC_TIMER_TSC_N

TSC to local APIC timer frequency multiplier (N)

CONFIG_APPLICATION_DEFINED_SYSCALL

Scan additional folders inside application source folder for application defined syscalls.

CONFIG_APPLICATION_INIT_PRIORITY

This priority level is for end-user drivers such as sensors and display which have no inward dependencies.

CONFIG_APP_LINK_WITH_FS

Add FS header files to the ‘app’ include path. It may be disabled if the include paths for FS are causing aliasing issues for ‘app’.

CONFIG_APP_LINK_WITH_LVGL

Add LVGL header files to the ‘app’ include path. It may be disabled if the include paths for LVGL are causing aliasing issues for ‘app’.

CONFIG_APP_LINK_WITH_MBEDTLS

Add MBEDTLS header files to the ‘app’ include path. It may be disabled if the include paths for MBEDTLS are causing aliasing issues for ‘app’.

CONFIG_APP_LINK_WITH_MCUMGR

Add MCUMGR header files to the ‘app’ include path. It may be disabled if the include paths for MCUMGR are causing aliasing issues for ‘app’.

CONFIG_APP_LINK_WITH_POSIX_SUBSYS

Add POSIX subsystem header files to the ‘app’ include path.

CONFIG_ARC

ARC architecture

CONFIG_ARCH

System architecture string.

CONFIG_ARCH_CACHE_FLUSH_DETECT

CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT

It’s possible that an architecture port cannot or does not want to use the provided k_busy_wait(), but instead must do something custom. It must enable this option in that case.

CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN

It’s possible that an architecture port cannot use _Swap() to swap to the _main() thread, but instead must do something custom. It must enable this option in that case.

CONFIG_ARCH_HAS_EXECUTABLE_PAGE_BIT

CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION

CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT

CONFIG_ARCH_HAS_RAMFUNC_SUPPORT

CONFIG_ARCH_HAS_STACK_PROTECTION

CONFIG_ARCH_HAS_THREAD_ABORT

CONFIG_ARCH_HAS_TRUSTED_EXECUTION

CONFIG_ARCH_HAS_USERSPACE

CONFIG_ARCH_LOG_LEVEL

CONFIG_ARCH_LOG_LEVEL_DBG

Debug

CONFIG_ARCH_LOG_LEVEL_ERR

Error

CONFIG_ARCH_LOG_LEVEL_INF

Info

CONFIG_ARCH_LOG_LEVEL_OFF

Off

CONFIG_ARCH_LOG_LEVEL_WRN

Warning

CONFIG_ARCH_POSIX

POSIX (native) architecture

CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE

In bytes, stack size for Zephyr threads meant only for the POSIX architecture. (In this architecture only part of the thread status is kept in the Zephyr thread stack, the real stack is the native underlying pthread stack. Therefore the allocated stack can be limited to this size)

CONFIG_ARCH_SW_ISR_TABLE_ALIGN

This option controls alignment size of generated _sw_isr_table. Some architecture needs a software ISR table to be aligned to architecture specific size. The default size is 0 for no alignment.

CONFIG_ARCV2_INTERRUPT_UNIT

The ARCv2 interrupt unit has 16 allocated exceptions associated with vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. The interrupt unit is optional in the ARCv2-based processors. When building a processor, you can configure the processor to include an interrupt unit. The ARCv2 interrupt unit is highly programmable.

CONFIG_ARCV2_TIMER

This module implements a kernel device driver for the ARCv2 processor timer 0 and provides the standard “system clock driver” interfaces.

CONFIG_ARCV2_TIMER_IRQ_PRIORITY

This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority.

CONFIG_ARC_CONNECT

ARC is configured with ARC CONNECT which is a hardware for connecting multi cores.

CONFIG_ARC_CORE_MPU

ARC core MPU functionalities

CONFIG_ARC_EXCEPTION_DEBUG

Print human-readable information about exception vectors, cause codes, and parameters, at a cost of code/data size for the human-readable strings.

CONFIG_ARC_EXCEPTION_STACK_SIZE

Size in bytes of exception handling stack which is at the top of interrupt stack to get smaller memory footprint because exception is not frequent. To reduce the impact on interrupt handling, especially nested interrupt, it cannot be too large.

CONFIG_ARC_FIRQ

Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts with highest priority, status32 and pc will be saved in aux regs, other regs will be saved according to the number of register bank; If FIRQ is disabled, the handle of interrupts with highest priority will be same with other interrupts.

CONFIG_ARC_FIRQ_STACK

Use separate stack for FIRQ handing. When the fast irq is also a direct irq, this will get the minimal interrupt latency.

CONFIG_ARC_FIRQ_STACK_SIZE

The size of firq stack.

CONFIG_ARC_HAS_ACCL_REGS

Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process

CONFIG_ARC_HAS_SECURE

This option is enabled when ARC core supports secure mode

CONFIG_ARC_HAS_STACK_CHECKING

ARC is configured with STACK_CHECKING which is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected.

CONFIG_ARC_MPU

Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D)

CONFIG_ARC_MPU_ENABLE

Enable MPU

CONFIG_ARC_MPU_VER

ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes; For MPU v3, the minimum region is 32 bytes

CONFIG_ARC_NORMAL_FIRMWARE

This option indicates that we are building a Zephyr image that is intended to execute in normal mode. Execution of this image is triggered by secure firmware that executes in secure mode. The option is only applicable to ARC processors that implement the SecureShield.

This option enables Zephyr to include code that executes in normal mode only, as well as to exclude code that is designed to execute only in secure mode.

Code executing in normal mode has no access to secure resources of the ARC processors, and, therefore, it shall avoid accessing them.

CONFIG_ARC_SECURE_FIRMWARE

This option indicates that we are building a Zephyr image that is intended to execute in secure mode. The option is only applicable to ARC processors that implement the SecureShield.

This option enables Zephyr to include code that executes in secure mode, as well as to exclude code that is designed to execute only in normal mode.

Code executing in secure mode has access to both the secure and normal resources of the ARC processors.

CONFIG_ARC_STACK_CHECKING

Use ARC STACK_CHECKING to do stack protection

CONFIG_ARC_STACK_PROTECTION

This option enables either: - The ARC stack checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the ARC stack checking is prioritized over the MPU-based stack guard.

CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS

ARC EM cores w/o secure shield 2+2 mode support might be configured to support unaligned memory access which is then disabled by default. Enable unaligned access in hardware and make software to use it.

CONFIG_ARM

ARM architecture

CONFIG_ARMV6_M_ARMV8_M_BASELINE

This option signifies the use of an ARMv6-M processor implementation, or the use of an ARMv8-M processor supporting the Baseline implementation.

Notes: - A Processing Element (PE) without the Main Extension is also referred to as a Baseline Implementation. A Baseline implementation has a subset of the instructions, registers, and features, of a Mainline implementation. - ARMv6-M compatibility is provided by all ARMv8-M implementations.

CONFIG_ARMV7_EXCEPTION_STACK_SIZE

This option specifies the size of the stack used by the undefined instruction and data abort exception handlers.

CONFIG_ARMV7_FIQ_STACK_SIZE

This option specifies the size of the stack used by the FIQ handler.

CONFIG_ARMV7_M_ARMV8_M_FP

This option signifies the use of an ARMv7-M processor implementation, or the use of an ARMv8-M processor implementation supporting the Floating-Point Extension.

CONFIG_ARMV7_M_ARMV8_M_MAINLINE

This option signifies the use of an ARMv7-M processor implementation, or the use of a backwards-compatible ARMv8-M processor implementation supporting the Main Extension.

Notes: - A Processing Element (PE) with the Main Extension is also referred to as a Mainline Implementation. - ARMv7-M compatibility requires the Main Extension.

From https://developer.arm.com/products/architecture/m-profile: The Main Extension provides backwards compatibility with ARMv7-M.

CONFIG_ARMV7_R

This option signifies the use of an ARMv7-R processor implementation.

From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: The Armv7-R architecture implements a traditional Arm architecture with multiple modes and supports a Protected Memory System Architecture (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32) and Thumb (T32) instruction sets.

CONFIG_ARMV7_R_FP

This option signifies the use of an ARMv7-R processor implementation supporting the Floating-Point Extension.

CONFIG_ARMV7_SVC_STACK_SIZE

This option specifies the size of the stack used by the SVC handler.

CONFIG_ARMV7_SYS_STACK_SIZE

This option specifies the size of the stack used by the system mode.

CONFIG_ARMV8_M_BASELINE

This option signifies the use of an ARMv8-M processor implementation.

ARMv8-M Baseline includes additional features not present in the ARMv6-M architecture.

CONFIG_ARMV8_M_DSP

This option signifies the use of an ARMv8-M processor implementation supporting the DSP Extension.

CONFIG_ARMV8_M_MAINLINE

This option signifies the use of an ARMv8-M processor implementation, supporting the Main Extension.

ARMv8-M Main Extension includes additional features not present in the ARMv7-M architecture.

CONFIG_ARMV8_M_SE

This option signifies the use of an ARMv8-M processor implementation (Baseline or Mainline) supporting the Security Extensions.

CONFIG_ARM_CLOCK_CONTROL_DEV_NAME

Configure Clock Config Device name

CONFIG_ARM_DIV

ARM clock divider

CONFIG_ARM_ENTRY_VENEERS_LIB_NAME

Library file to find the symbol table for the entry veneers. The library will typically come from building the Secure Firmware that contains secure entry functions, and allows the Non-Secure Firmware to call into the Secure Firmware.

CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS

Option indicates that ARM Secure Firmware contains Secure Entry functions that may be called from Non-Secure state. Secure Entry functions must be located in Non-Secure Callable memory regions.

CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS

Option indicates that ARM Non-Secure Firmware uses Secure Entry functions provided by the Secure Firmware. The Secure Firmware must be configured to provide these functions.

CONFIG_ARM_MPU

MCU implements Memory Protection Unit.

Notes: The ARMv6-M and ARMv8-M MPU architecture requires a power-of-two alignment of MPU region base address and size.

The NXP MPU as well as the ARMv8-M MPU do not require MPU regions to have power-of-two alignment for base address and region size.

The ARMv8-M MPU requires the active MPU regions be non-overlapping. As a result of this, the ARMv8-M MPU needs to fully partition the memory map when programming dynamic memory regions (e.g. PRIV stack guard, user thread stack, and application memory domains), if the system requires PRIV access policy different from the access policy of the ARMv8-M background memory map. The application developer may enforce full PRIV (kernel) memory partition by enabling the CONFIG_MPU_GAP_FILLING option. By not enforcing full partition, MPU may leave part of kernel SRAM area covered only by the default ARMv8-M memory map. This is fine for User Mode, since the background ARM map does not allow nPRIV access at all. However, since the background map policy allows instruction fetches by privileged code, forcing this Kconfig option off prevents the system from directly triggering MemManage exceptions upon accidental attempts to execute code from SRAM in XIP builds. Since this does not compromise User Mode, we make the skipping of full partitioning the default behavior for the ARMv8-M MPU driver.

CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE

Minimum size (and alignment) of an ARM MPU region. Use this symbol to guarantee minimum size and alignment of MPU regions. A minimum 4-byte alignment is enforced in ARM builds without support for Memory Protection.

CONFIG_ARM_NONSECURE_FIRMWARE

This option indicates that we are building a Zephyr image that is intended to execute in Non-Secure state. Execution of this image is triggered by Secure firmware that executes in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension.

This option enables Zephyr to include code that executes in Non-Secure state only, as well as to exclude code that is designed to execute only in Secure state.

Code executing in Non-Secure state has no access to Secure resources of the Cortex-M MCU, and, therefore, it shall avoid accessing them.

CONFIG_ARM_NSC_REGION_BASE_ADDRESS

Start address of Non-Secure Callable section.

Notes: - The default value (i.e. when the user does not configure the option explicitly) instructs the linker script to place the Non-Secure Callable section, automatically, inside the .text area. - Certain requirements/restrictions may apply regarding the size and the alignment of the starting address for a Non-Secure Callable section, depending on the available security attribution unit (SAU or IDAU) for a given SOC.

CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI

Force NMI, HardFault, and BusFault (in Mainline ARMv8-M) exceptions as Secure exceptions.

CONFIG_ARM_SECURE_FIRMWARE

This option indicates that we are building a Zephyr image that is intended to execute in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension.

This option enables Zephyr to include code that executes in Secure state, as well as to exclude code that is designed to execute only in Non-secure state.

Code executing in Secure state has access to both the Secure and Non-Secure resources of the Cortex-M MCU.

Code executing in Non-Secure state may trigger Secure Faults, if Secure MCU resources are accessed from the Non-Secure state. Secure Faults may only be handled by code executing in Secure state.

CONFIG_ARM_STACK_PROTECTION

This option enables either: - The built-in Stack Pointer limit checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the built-in Stack Pointer limit checking is prioritized over the MPU-based stack guard. The developer still has the option to manually select the MPU-based stack guard, if this is desired.

CONFIG_ARM_TRUSTZONE_M

Platform has support for ARM TrustZone-M.

CONFIG_ASAN

Builds Zephyr with Address Sanitizer enabled. This is currently only supported by boards based on the posix architecture, and requires a recent-ish compiler with the -fsanitize=address command line option, and the libasan library.

Note that at exit leak detection is disabled for 64-bit boards when GCC is used due to potential risk of a deadlock in libasan. This behavior can be changes by adding leak_check_at_exit=1 to the environment variable ASAN_OPTIONS.

CONFIG_ASF

CONFIG_ASSERT

This enables the __ASSERT() macro in the kernel code. If an assertion fails, the policy for what to do is controlled by the implementation of the assert_post_action() function, which by default will trigger a fatal error.

Disabling this option will cause assertions to compile to nothing, improving performance and system footprint.

CONFIG_ASSERT_LEVEL

This option specifies the assertion level used by the __ASSERT() macro. It can be set to one of three possible values:

Level 0: off Level 1: on + warning in every file that includes __assert.h Level 2: on + no warning

CONFIG_ASSERT_NO_FILE_INFO

This option removes the name and the path of the source file in which the assertion occurred. Enabling this will save target code space, and thus may be necessary for tiny targets.

CONFIG_ATMEL_WINC1500

CONFIG_ATOMIC_OPERATIONS_BUILTIN

Use the compiler builtin functions for atomic operations. This is the preferred method. However, support for all arches in GCC is incomplete.

CONFIG_ATOMIC_OPERATIONS_C

Use atomic operations routines that are implemented entirely in C by locking interrupts. Selected by architectures which either do not have support for atomic operations in their instruction set, or haven’t been implemented yet during bring-up, and also the compiler does not have support for the atomic __sync_* builtins.

CONFIG_ATOMIC_OPERATIONS_CUSTOM

Use when there isn’t support for compiler built-ins, but you have written optimized assembly code under arch/ which implements these.

CONFIG_AUDIO

Enable support for Audio

CONFIG_AUDIO_CODEC

Enable Audio Codec Driver Configuration

CONFIG_AUDIO_CODEC_INIT_PRIORITY

Audio codec device driver initialization priority.

CONFIG_AUDIO_CODEC_LOG_LEVEL

CONFIG_AUDIO_CODEC_LOG_LEVEL_DBG

Debug

CONFIG_AUDIO_CODEC_LOG_LEVEL_ERR

Error

CONFIG_AUDIO_CODEC_LOG_LEVEL_INF

Info

CONFIG_AUDIO_CODEC_LOG_LEVEL_OFF

Off

CONFIG_AUDIO_CODEC_LOG_LEVEL_WRN

Warning

CONFIG_AUDIO_DMIC

Enable Digital Microphone Driver Configuration

CONFIG_AUDIO_DMIC_INIT_PRIORITY

Audio Digital Microphone device driver initialization priority.

CONFIG_AUDIO_DMIC_LOG_LEVEL

CONFIG_AUDIO_DMIC_LOG_LEVEL_DBG

Debug

CONFIG_AUDIO_DMIC_LOG_LEVEL_ERR

Error

CONFIG_AUDIO_DMIC_LOG_LEVEL_INF

Info

CONFIG_AUDIO_DMIC_LOG_LEVEL_OFF

Off

CONFIG_AUDIO_DMIC_LOG_LEVEL_WRN

Warning

CONFIG_AUDIO_INTEL_DMIC

Enable Intel digital PDM microphone driver

CONFIG_AUDIO_MPXXDTYY

Enable MPXXDTYY microphone support on the selected board

CONFIG_AUDIO_TLV320DAC

Enable TLV320DAC support on the selected board

CONFIG_BASE64

Enable base64 encoding and decoding functionality

CONFIG_BATTERY_SENSE

Enable the battery sense circuit

CONFIG_BIG_ENDIAN

This option tells the build system that the target system is big-endian. Little-endian architecture is the default and should leave this option unselected. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it. The option is used to select linker script OUTPUT_FORMAT and command line option for gen_isr_tables.py.

CONFIG_BLUETOOTH_BULK_EP_MPS

Bluetooth device class bulk endpoint size

CONFIG_BLUETOOTH_INT_EP_MPS

Bluetooth device class interrupt endpoint size

CONFIG_BMA280

Enable driver for BMA280 I2C-based triaxial accelerometer sensor family.

CONFIG_BMA280_CHIP_BMA280

Choose this option to enable the BMA280 chip.

CONFIG_BMA280_CHIP_BMC150_ACCEL

Choose this option to enable the accelerometer of the BMC150 chip.

CONFIG_BMA280_GPIO_DEV_NAME

The device name of the GPIO device to which the chip’s interrupt pins are connected.

CONFIG_BMA280_GPIO_PIN_NUM

The number of the GPIO on which the interrupt signal from the chip will be received.

CONFIG_BMA280_I2C_ADDR

I2C address of the BMA280 sensor.

0x10: Use if the SDO pin is pulled to GND. 0x10: Use if the SDO pin is pulled to VDDIO. 0x18: Use if the SDO pin is pulled to GND. 0x19: Use if the SDO pin is pulled to VDDIO.

CONFIG_BMA280_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which chip is connected.

CONFIG_BMA280_NAME

Device name with which the sensor is identified.

CONFIG_BMA280_PMU_BW_1

7.81Hz

CONFIG_BMA280_PMU_BW_2

15.63HZ

CONFIG_BMA280_PMU_BW_3

31.25Hz

CONFIG_BMA280_PMU_BW_4

62.5Hz

CONFIG_BMA280_PMU_BW_5

125Hz

CONFIG_BMA280_PMU_BW_6

250HZ

CONFIG_BMA280_PMU_BW_7

500Hz

CONFIG_BMA280_PMU_BW_8

unfiltered

CONFIG_BMA280_PMU_RANGE_16G

+/-16g

CONFIG_BMA280_PMU_RANGE_2G

+/-2g

CONFIG_BMA280_PMU_RANGE_4G

+/-4g

CONFIG_BMA280_PMU_RANGE_8G

+/-8g

CONFIG_BMA280_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_BMA280_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_BMA280_TRIGGER

CONFIG_BMA280_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMA280_TRIGGER_NONE

No trigger

CONFIG_BMA280_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMC150_MAGN

Enable driver for BMC150 I2C-based magnetometer sensor.

CONFIG_BMC150_MAGN_PRESET_ENHANCED_REGULAR

Enhanced regular (15, 27, 10)

CONFIG_BMC150_MAGN_PRESET_HIGH_ACCURACY

High accuracy (47, 83, 20)

CONFIG_BMC150_MAGN_PRESET_LOW_POWER

Low power (3, 3, 10)

CONFIG_BMC150_MAGN_PRESET_REGULAR

Regular (9, 15, 10)

CONFIG_BMC150_MAGN_SAMPLING_RATE_RUNTIME

Enable alteration of sampling rate attribute at runtime.

CONFIG_BMC150_MAGN_SAMPLING_REP_XY

Enable alteration of XY oversampling at runtime.

CONFIG_BMC150_MAGN_SAMPLING_REP_Z

Enable alteration of Z oversampling at runtime.

CONFIG_BMC150_MAGN_TRIGGER

Enable triggers for BMC150 magnetometer

CONFIG_BMC150_MAGN_TRIGGER_DRDY

Enable data ready interrupt for BMC150 magnetometer

CONFIG_BMC150_MAGN_TRIGGER_THREAD_STACK

Specify the internal thread stack size.

CONFIG_BME280

Enable driver for BME280 I2C-based or SPI-based temperature and pressure sensor.

CONFIG_BME280_FILTER_16

16

CONFIG_BME280_FILTER_2

2

CONFIG_BME280_FILTER_4

4

CONFIG_BME280_FILTER_8

8

CONFIG_BME280_FILTER_OFF

filter off

CONFIG_BME280_HUMIDITY_OVER_16X

x16

CONFIG_BME280_HUMIDITY_OVER_1X

x1

CONFIG_BME280_HUMIDITY_OVER_2X

x2

CONFIG_BME280_HUMIDITY_OVER_4X

x4

CONFIG_BME280_HUMIDITY_OVER_8X

x8

CONFIG_BME280_PRESS_OVER_16X

x16

CONFIG_BME280_PRESS_OVER_1X

x1

CONFIG_BME280_PRESS_OVER_2X

x2

CONFIG_BME280_PRESS_OVER_4X

x4

CONFIG_BME280_PRESS_OVER_8X

x8

CONFIG_BME280_STANDBY_05MS

0.5ms

CONFIG_BME280_STANDBY_1000MS

1000ms

CONFIG_BME280_STANDBY_125MS

125ms

CONFIG_BME280_STANDBY_2000MS

2000ms BMP280 / 10ms BME280

CONFIG_BME280_STANDBY_250MS

250ms

CONFIG_BME280_STANDBY_4000MS

4000ms BMP280 / 20ms BME280

CONFIG_BME280_STANDBY_500MS

500ms

CONFIG_BME280_STANDBY_62MS

62.5ms

CONFIG_BME280_TEMP_OVER_16X

x16

CONFIG_BME280_TEMP_OVER_1X

x1

CONFIG_BME280_TEMP_OVER_2X

x2

CONFIG_BME280_TEMP_OVER_4X

x4

CONFIG_BME280_TEMP_OVER_8X

x8

CONFIG_BME680

Enable driver for BME680 I2C-based based temperature, pressure, humidity and gas sensor.

CONFIG_BME680_FILTER_128

128

CONFIG_BME680_FILTER_16

16

CONFIG_BME680_FILTER_2

2

CONFIG_BME680_FILTER_32

32

CONFIG_BME680_FILTER_4

4

CONFIG_BME680_FILTER_64

64

CONFIG_BME680_FILTER_8

8

CONFIG_BME680_FILTER_OFF

filter off

CONFIG_BME680_HEATR_DUR_LP

197

CONFIG_BME680_HEATR_DUR_ULP

1943

CONFIG_BME680_HEATR_TEMP_LP

320

CONFIG_BME680_HEATR_TEMP_ULP

400

CONFIG_BME680_HUMIDITY_OVER_16X

x16

CONFIG_BME680_HUMIDITY_OVER_1X

x1

CONFIG_BME680_HUMIDITY_OVER_2X

x2

CONFIG_BME680_HUMIDITY_OVER_4X

x4

CONFIG_BME680_HUMIDITY_OVER_8X

x8

CONFIG_BME680_PRESS_OVER_16X

x16

CONFIG_BME680_PRESS_OVER_1X

x1

CONFIG_BME680_PRESS_OVER_2X

x2

CONFIG_BME680_PRESS_OVER_4X

x4

CONFIG_BME680_PRESS_OVER_8X

x8

CONFIG_BME680_TEMP_OVER_16X

x16

CONFIG_BME680_TEMP_OVER_1X

x1

CONFIG_BME680_TEMP_OVER_2X

x2

CONFIG_BME680_TEMP_OVER_4X

x4

CONFIG_BME680_TEMP_OVER_8X

x8

CONFIG_BMG160

Enable Bosch BMG160 gyroscope support.

CONFIG_BMG160_I2C_SPEED_FAST

Fast bus speed of up to 400KHz.

CONFIG_BMG160_I2C_SPEED_STANDARD

Standard bus speed of up to 100kHz.

CONFIG_BMG160_ODR_100

100 Hz

CONFIG_BMG160_ODR_1000

1000 Hz

CONFIG_BMG160_ODR_200

200 Hz

CONFIG_BMG160_ODR_2000

2000 Hz

CONFIG_BMG160_ODR_400

400 Hz

CONFIG_BMG160_ODR_RUNTIME

Set at runtime.

CONFIG_BMG160_RANGE_1000DPS

1000 DPS

CONFIG_BMG160_RANGE_125DPS

125 DPS

CONFIG_BMG160_RANGE_2000DPS

2000 DPS

CONFIG_BMG160_RANGE_250DPS

250 DPS

CONFIG_BMG160_RANGE_500DPS

500 DPS

CONFIG_BMG160_RANGE_RUNTIME

Set at runtime.

CONFIG_BMG160_THREAD_PRIORITY

The priority of the thread used for handling interrupts.

CONFIG_BMG160_THREAD_STACK_SIZE

The thread stack size.

CONFIG_BMG160_TRIGGER

CONFIG_BMG160_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMG160_TRIGGER_NONE

No trigger

CONFIG_BMG160_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMI160

Enable Bosch BMI160 inertial measurement unit that provides acceleration and angular rate measurements.

CONFIG_BMI160_ACCEL_ODR_100

100 Hz

CONFIG_BMI160_ACCEL_ODR_1600

1600 Hz

CONFIG_BMI160_ACCEL_ODR_200

200 Hz

CONFIG_BMI160_ACCEL_ODR_25

25 Hz

CONFIG_BMI160_ACCEL_ODR_25_16

1.56 Hz

CONFIG_BMI160_ACCEL_ODR_25_2

12.5 Hz

CONFIG_BMI160_ACCEL_ODR_25_32

0.78 Hz

CONFIG_BMI160_ACCEL_ODR_25_4

6.25 Hz

CONFIG_BMI160_ACCEL_ODR_25_8

3.125 Hz

CONFIG_BMI160_ACCEL_ODR_400

400 Hz

CONFIG_BMI160_ACCEL_ODR_50

50 Hz

CONFIG_BMI160_ACCEL_ODR_800

800 Hz

CONFIG_BMI160_ACCEL_ODR_RUNTIME

Set at runtime.

CONFIG_BMI160_ACCEL_PMU_LOW_POWER

low power

CONFIG_BMI160_ACCEL_PMU_NORMAL

normal

CONFIG_BMI160_ACCEL_PMU_RUNTIME

Set at runtime.

CONFIG_BMI160_ACCEL_PMU_SUSPEND

suspended/not used

CONFIG_BMI160_ACCEL_RANGE_16G

16G

CONFIG_BMI160_ACCEL_RANGE_2G

2G

CONFIG_BMI160_ACCEL_RANGE_4G

4G

CONFIG_BMI160_ACCEL_RANGE_8G

8G

CONFIG_BMI160_ACCEL_RANGE_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_ODR_100

100 Hz

CONFIG_BMI160_GYRO_ODR_1600

1600 Hz

CONFIG_BMI160_GYRO_ODR_200

200 Hz

CONFIG_BMI160_GYRO_ODR_25

25 Hz

CONFIG_BMI160_GYRO_ODR_3200

3200 Hz

CONFIG_BMI160_GYRO_ODR_400

400 Hz

CONFIG_BMI160_GYRO_ODR_50

50 Hz

CONFIG_BMI160_GYRO_ODR_800

800 Hz

CONFIG_BMI160_GYRO_ODR_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_PMU_FAST_STARTUP

fast start-up

CONFIG_BMI160_GYRO_PMU_NORMAL

normal

CONFIG_BMI160_GYRO_PMU_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_PMU_SUSPEND

suspended/not used

CONFIG_BMI160_GYRO_RANGE_1000DPS

1000 DPS

CONFIG_BMI160_GYRO_RANGE_125DPS

125 DPS

CONFIG_BMI160_GYRO_RANGE_2000DPS

2000 DPS

CONFIG_BMI160_GYRO_RANGE_250DPS

250 DPS

CONFIG_BMI160_GYRO_RANGE_500DPS

500 DPS

CONFIG_BMI160_GYRO_RANGE_RUNTIME

Set at runtime.

CONFIG_BMI160_THREAD_PRIORITY

The priority of the thread used for handling interrupts.

CONFIG_BMI160_THREAD_STACK_SIZE

The thread stack size.

CONFIG_BMI160_TRIGGER

CONFIG_BMI160_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMI160_TRIGGER_NONE

No trigger

CONFIG_BMI160_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMM150

Enable driver for BMM150 I2C-based Geomagnetic sensor.

CONFIG_BMM150_PRESET_ENHANCED_REGULAR

Enhanced regular (15, 27, 10)

CONFIG_BMM150_PRESET_HIGH_ACCURACY

High accuracy (47, 83, 20)

CONFIG_BMM150_PRESET_LOW_POWER

Low power (3, 3, 10)

CONFIG_BMM150_PRESET_REGULAR

Regular (9, 15, 10)

CONFIG_BMM150_SAMPLING_RATE_RUNTIME

Enable alteration of sampling rate attribute at runtime.

CONFIG_BMM150_SAMPLING_REP_XY

Enable alteration of XY oversampling at runtime.

CONFIG_BMM150_SAMPLING_REP_Z

Enable alteration of Z oversampling at runtime.

CONFIG_BOARD

This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). The Board is the first location where we search for a linker.ld file, if not found we look for the linker file in soc/<arch>/<family>/<series>

CONFIG_BOARD_96B_ARGONKEY

96Boards Argonkey

CONFIG_BOARD_96B_AVENGER96

96Boards Avenger96 Board

CONFIG_BOARD_96B_CARBON

96Boards Carbon (STM32F401)

CONFIG_BOARD_96B_CARBON_NRF51

96Boards Carbon (nRF51)

CONFIG_BOARD_96B_MEERKAT96

96Boards Meerkat96 board

CONFIG_BOARD_96B_NEONKEY

96Boards Neonkey

CONFIG_BOARD_96B_NITROGEN

96Boards Nitrogen

CONFIG_BOARD_96B_STM32_SENSOR_MEZ

96Boards STM32 Sensor Mezzanine Board

CONFIG_BOARD_96B_WISTRIO

96boards WisTrio Development Board

CONFIG_BOARD_ACRN

ACRN User OS

CONFIG_BOARD_ACTINIUS_ICARUS

Actinius Icarus

CONFIG_BOARD_ACTINIUS_ICARUS_NS

Actinius Icarus Non-Secure

CONFIG_BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO

Adafruit Feather M0 Basic Proto

CONFIG_BOARD_ADAFRUIT_TRINKET_M0

Adafruit Trinket M0

CONFIG_BOARD_ALTERA_MAX10

Altera MAX10 Board

CONFIG_BOARD_ARDUINO_DUE

Arduino Due Board

CONFIG_BOARD_ARDUINO_ZERO

Arduino Zero

CONFIG_BOARD_ATSAMD20_XPRO

SAM D20 Xplained Pro

CONFIG_BOARD_ATSAMD21_XPRO

SAM D21 Xplained Pro

CONFIG_BOARD_ATSAMR21_XPRO

SAM R21 Xplained Pro

CONFIG_BOARD_BBC_MICROBIT

BBC MICRO:BIT

CONFIG_BOARD_BL652_DVK

BL652 DVK

CONFIG_BOARD_BL654_DVK

BL654 DVK

CONFIG_BOARD_B_L072Z_LRWAN1

STMicroelectronics B-L072Z-LRWAN1 Discovery kit

CONFIG_BOARD_CC1352R1_LAUNCHXL

TI CC1352R1 LaunchXL

CONFIG_BOARD_CC2650_SENSORTAG

TI CC2650 SensorTag

CONFIG_BOARD_CC26X2R1_LAUNCHXL

TI CC26x2R1 LaunchXL

CONFIG_BOARD_CC3220SF_LAUNCHXL

TI CC3220SF LAUNCHXL

CONFIG_BOARD_CC3235SF_LAUNCHXL

TI CC3235SF LAUNCHXL

CONFIG_BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY

Initialization priority for the CCS_VDD power rail. This powers the CCS811 gas sensor. The value has to be greater than BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY.

CONFIG_BOARD_COLIBRI_IMX7D_M4

Toradex Colibri iMX7 Dual

CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M0

PSoC6 WiFi-BT Pioneer Kit M0

CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M4

PSoC6 WiFi-BT Pioneer Kit M4

CONFIG_BOARD_DECAWAVE_DWM1001_DEV

Decawave DWM1001-DEV

CONFIG_BOARD_DEGU_EVK

DEGU_EVK

CONFIG_BOARD_DEPRECATED

This hidden option is set in the board configuration and indicates the Zephyr release that the board configuration will be removed. When set, any build for that board will generate a clearly visible deprecation warning.

CONFIG_BOARD_DISCO_L475_IOT1

Discovery IoT L475 Development Board

CONFIG_BOARD_DRAGINO_LSN50

Dragino LSN50 Sensor Node

CONFIG_BOARD_EFM32HG_SLSTK3400A

SiLabs EFM32HG-SLSTK3400A (Happy Gecko)

CONFIG_BOARD_EFM32PG_STK3402A

SiLabs EFM32PG-STK3402A (Pearl Gecko)

CONFIG_BOARD_EFM32WG_STK3800

SiLabs EFM32WG-STK3800 (Wonder Gecko)

CONFIG_BOARD_EFR32MG_SLTB004A

SiLabs EFR32MG-SLTB004A (Thunderboard Sense 2)

CONFIG_BOARD_EFR32_SLWSTK6061A

SiLabs EFR32-SLWSTK6061A (Flex Gecko)

CONFIG_BOARD_EMSDP

The ARC EM Software Development Platform (emsdp) is an FPGA based development platform intended to support ARC licenses in developing their software for the ARC EM processor family and ARC EM Subsystems. It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D processors. ARC EM Enhanced Security Package (ESP) and ARC EM Subsystems (DFSS, SCSS, DSS) are also supported.

CONFIG_BOARD_EM_STARTERKIT

The DesignWare ARC EM Starter Kit board is a board that can host up to 3 different SOC FPGA bit files. Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. EM9D using CCM memories and is a Harvard Architecture. EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. EM7D of EMSK 2.3 supports secure mode.

CONFIG_BOARD_EM_STARTERKIT_R22

2.2

CONFIG_BOARD_EM_STARTERKIT_R23

2.3

CONFIG_BOARD_ENABLE_DCDC

Enable DCDC mode

CONFIG_BOARD_ENABLE_DCDC_APP

Enable Application MCU DCDC converter

CONFIG_BOARD_ENABLE_DCDC_HV

Enable High Voltage DCDC converter

CONFIG_BOARD_ENABLE_DCDC_NET

Enable Network MCU DCDC converter

CONFIG_BOARD_ESP32

ESP32 Development Board

CONFIG_BOARD_FRDM_K22F

NXP FRDM-K22F

CONFIG_BOARD_FRDM_K64F

Freescale FRDM-K64F

CONFIG_BOARD_FRDM_K82F

NXP FRDM-K82F

CONFIG_BOARD_FRDM_KL25Z

NXP FRDM-KL25Z

CONFIG_BOARD_FRDM_KW41Z

NXP FRDM-KW41Z

CONFIG_BOARD_GPMRB

Gordon Peak MRB

CONFIG_BOARD_HAS_NRF5_BOOTLOADER

If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader.

CONFIG_BOARD_HEXIWEAR_K64

NXP Hexiwear K64

CONFIG_BOARD_HEXIWEAR_KW40Z

Hexiwear KW40Z

CONFIG_BOARD_HIFIVE1

HiFive1 target

CONFIG_BOARD_HIFIVE1_REVB

HiFive1 Rev B target

CONFIG_BOARD_HOLYIOT_YJ16019

Holyiot YJ-16019

CONFIG_BOARD_HSDK

The DesignWare ARC HS Development Kit is a ready-to-use platform for rapid software development on the ARC HS3x family of processors. It supports single- and multi-core ARC HS34, HS36 and HS38 processors and offers a wide range of interfaces

CONFIG_BOARD_ICARUS_LOG_LEVEL

CONFIG_BOARD_ICARUS_LOG_LEVEL_DBG

Debug

CONFIG_BOARD_ICARUS_LOG_LEVEL_ERR

Error

CONFIG_BOARD_ICARUS_LOG_LEVEL_INF

Info

CONFIG_BOARD_ICARUS_LOG_LEVEL_OFF

Off

CONFIG_BOARD_ICARUS_LOG_LEVEL_WRN

Warning

CONFIG_BOARD_INIT_PRIORITY

Board initialization priority. This must be bigger than GPIO_GECKO_COMMON_INIT_PRIORITY.

CONFIG_BOARD_INTEL_S1000_CRB

Xtensa on Intel_S1000

CONFIG_BOARD_IOTDK

The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC’s 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs.

CONFIG_BOARD_LITEX_VEXRISCV

Board with LiteX/VexRiscV CPU

CONFIG_BOARD_LPCXPRESSO54114_M0

NXP LPCXPRESSO-54114 M0

CONFIG_BOARD_LPCXPRESSO54114_M4

NXP LPCXPRESSO-54114 M4

CONFIG_BOARD_LPCXPRESSO55S69_CPU0

NXP LPCXPRESSO-55S69 [CPU0]

CONFIG_BOARD_LPCXPRESSO55S69_CPU1

NXP LPCXPRESSO-55S69 [CPU1]

CONFIG_BOARD_M2GL025_MIV

Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU

CONFIG_BOARD_MEC1501MODULAR_ASSY6885

Microchip MEC1501 Modular ASSY 6885 Development board

CONFIG_BOARD_MEC15XXEVB_ASSY6853

Microchip MEC15XX EVB ASSY 6853 Development board

CONFIG_BOARD_MEC2016EVB_ASSY6797

Microchip MEC2016 EVB ASSY 6797 Development board

CONFIG_BOARD_MIKROE_MINI_M4_FOR_STM32

Mikroe MINI-M4 for STM32 Board

CONFIG_BOARD_MIMXRT1015_EVK

NXP MIMXRT1015-EVK

CONFIG_BOARD_MIMXRT1020_EVK

NXP MIMXRT1020-EVK

CONFIG_BOARD_MIMXRT1050_EVK

NXP MIMXRT1050-EVK

CONFIG_BOARD_MIMXRT1050_EVK_QSPI

NXP MIMXRT1050-EVK-QSPI

CONFIG_BOARD_MIMXRT1060_EVK

NXP MIMXRT1060-EVK

CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH

NXP MIMXRT1060-EVK-HYPERFLASH

CONFIG_BOARD_MIMXRT1064_EVK

NXP MIMXRT1064-EVK

CONFIG_BOARD_MINNOWBOARD

MinnowBoard Max

CONFIG_BOARD_MPS2_AN385

ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)

CONFIG_BOARD_MPS2_AN521

ARM Cortex-M33 SMM on V2M-MPS2 (AN521)

CONFIG_BOARD_MSP_EXP432P401R_LAUNCHXL

TI MSP-EXP432P401R LAUNCHXL

CONFIG_BOARD_MUSCA_A

ARM Cortex-M33 SMM on V2M-MUSCA

CONFIG_BOARD_MUSCA_B1

ARM Cortex-M33 SMM on V2M-MUSCA

CONFIG_BOARD_NATIVE_POSIX

CONFIG_BOARD_NATIVE_POSIX_32BIT

Will produce a console Linux process which can be executed natively as a 32-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout.

CONFIG_BOARD_NATIVE_POSIX_64BIT

Will produce a console Linux process which can be executed natively as a 64-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout.

CONFIG_BOARD_NRF51_BLE400

nRF51 BLE400

CONFIG_BOARD_NRF51_BLENANO

nRF51 BLENANO

CONFIG_BOARD_NRF51_PCA10028

nRF51 PCA10028

CONFIG_BOARD_NRF51_PCA10031

nRF51 PCA10031

CONFIG_BOARD_NRF51_VBLUNO51

nRF51 VBLUno51 BLE

CONFIG_BOARD_NRF52810_PCA10040

nRF52810 PCA10040

CONFIG_BOARD_NRF52811_PCA10056

nRF52811 PCA10056

CONFIG_BOARD_NRF52832_MDK

nRF52832-MDK

CONFIG_BOARD_NRF52833_PCA10100

NRF52833 PCA10100

CONFIG_BOARD_NRF52840_BLIP

Electronut Labs Blip

CONFIG_BOARD_NRF52840_GPIO_RESET

Use a GPIO pin to reset the nRF52840 controller and let it wait until all bytes traveling to the H4 device have been received and drained, thus ensuring communication can begin correctly.

CONFIG_BOARD_NRF52840_GPIO_RESET_PIN

GPIO pin on the nRF9160 used to reset the nRF52840.

CONFIG_BOARD_NRF52840_MDK

NRF52840-MDK

CONFIG_BOARD_NRF52840_PAPYR

NRF52840 PAPYR

CONFIG_BOARD_NRF52840_PCA10056

NRF52840 PCA10056

CONFIG_BOARD_NRF52840_PCA10059

NRF52840 PCA10059

CONFIG_BOARD_NRF52840_PCA10090

NRF52840 PCA10090

CONFIG_BOARD_NRF52_ADAFRUIT_FEATHER

nRF52 ADAFRUIT FEATHER

CONFIG_BOARD_NRF52_BLENANO2

nRF52 BLENANO2

CONFIG_BOARD_NRF52_BSIM

Will produce a console Linux process which can be executed natively. It needs the BabbleSim simulator both in compile time and to execute

CONFIG_BOARD_NRF52_PCA10040

nRF52 PCA10040

CONFIG_BOARD_NRF52_PCA20020

nRF52 PCA20020

CONFIG_BOARD_NRF52_SPARKFUN

nRF52 SPARKFUN

CONFIG_BOARD_NRF52_VBLUNO52

nRF52 VBLUno52

CONFIG_BOARD_NRF5340_DK_NRF5340_CPUAPP

nRF5340 DK nRF5340 Application MCU

CONFIG_BOARD_NRF5340_DK_NRF5340_CPUAPPNS

nRF5340 DK nRF5340 Application MCU non-secure

CONFIG_BOARD_NRF5340_DK_NRF5340_CPUNET

nRF5340 DK NRF5340 Network MCU

CONFIG_BOARD_NRF9160_PCA10090

nRF9160 PCA10090

CONFIG_BOARD_NRF9160_PCA10090NS

nRF9160 PCA10090 non-secure

CONFIG_BOARD_NSIM

The DesignWare ARC nSIM board is a virtual board based on the ARC nSIM simulator. It demonstrates the ARC core features and a console based on the legacy ARC UART model.

CONFIG_BOARD_NUCLEO_F030R8

NUCLEO-64 F030R8 Development Board

CONFIG_BOARD_NUCLEO_F070RB

NUCLEO-64 F070RB Development Board

CONFIG_BOARD_NUCLEO_F091RC

NUCLEO-64 F091RC Development Board

CONFIG_BOARD_NUCLEO_F103RB

NUCLEO-64 F103RB Development Board

CONFIG_BOARD_NUCLEO_F207ZG

NUCLEO-144 F207ZG Development Board

CONFIG_BOARD_NUCLEO_F302R8

NUCLEO-64 F302R8 Development Board

CONFIG_BOARD_NUCLEO_F334R8

NUCLEO-64 F334R8 Development Board

CONFIG_BOARD_NUCLEO_F401RE

NUCLEO-64 F401RE Development Board

CONFIG_BOARD_NUCLEO_F411RE

NUCLEO-64 F411RE Development Board

CONFIG_BOARD_NUCLEO_F412ZG

NUCLEO-144 F412ZG Development Board

CONFIG_BOARD_NUCLEO_F413ZH

NUCLEO-144 F413ZH Development Board

CONFIG_BOARD_NUCLEO_F429ZI

NUCLEO-144 F429ZI Development Board

CONFIG_BOARD_NUCLEO_F446RE

Nucleo F446RE Development Board

CONFIG_BOARD_NUCLEO_F746ZG

Nucleo F746ZG Development Board

CONFIG_BOARD_NUCLEO_F756ZG

Nucleo F756ZG Development Board

CONFIG_BOARD_NUCLEO_G071RB

NUCLEO-64 G071RB Development Board

CONFIG_BOARD_NUCLEO_G431RB

Nucleo G431RB Development Board

CONFIG_BOARD_NUCLEO_L053R8

NUCLEO-64 L053R8 Development Board

CONFIG_BOARD_NUCLEO_L073RZ

NUCLEO-64 L073RZ Development Board

CONFIG_BOARD_NUCLEO_L432KC

Nucleo L432KC Development Board

CONFIG_BOARD_NUCLEO_L476RG

Nucleo L476RG Development Board

CONFIG_BOARD_NUCLEO_L496ZG

Nucleo L496ZG Development Board

CONFIG_BOARD_NUCLEO_L4R5ZI

Nucleo L4R5ZI Development Board

CONFIG_BOARD_NUCLEO_WB55RG

Nucleo WB55RG Development Board

CONFIG_BOARD_ODROID_GO

ODROID-GO Game Kit

CONFIG_BOARD_OLIMEXINO_STM32

OLIMEXINO-STM32 Development Board

CONFIG_BOARD_OLIMEX_STM32_E407

OLIMEX-STM32-E407 Development Board

CONFIG_BOARD_OLIMEX_STM32_H407

OLIMEX-STM32-H407 Development Board

CONFIG_BOARD_OLIMEX_STM32_P405

OLIMEX-STM32-P405 Development Board

CONFIG_BOARD_PARTICLE_ARGON

Particle Argon Board

CONFIG_BOARD_PARTICLE_BORON

Particle Boron Board

CONFIG_BOARD_PARTICLE_XENON

Particle Xenon Board

CONFIG_BOARD_PCA10090_BUTTON0_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_BUTTON0_PHY

Route to buttons on the kit

CONFIG_BOARD_PCA10090_BUTTON1_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_BUTTON1_PHY

Route to buttons on the kit

CONFIG_BOARD_PCA10090_INTERFACE0_ARDUINO

Pin 0: nRF9160 P0.17 connects to A3 Pin 1: nRF9160 P0.18 connects to A4 Pin 2: nRF9160 P0.19 connects to A5

CONFIG_BOARD_PCA10090_INTERFACE0_MCU

This connects the following pins on the nRF9160 to pins on the nRF52840: Pin 0: nRF9160 P0.17 connects to nRF52840 P0.17 Pin 1: nRF9160 P0.18 connects to nRF52840 P0.20 Pin 2: nRF9160 P0.19 connects to nRF52840 P0.15

CONFIG_BOARD_PCA10090_INTERFACE1_MCU

Pin 3: nRF9160 P0.21 connects to nRF52840 P0.22 Pin 4: nRF9160 P0.22 connects to nRF52840 P1.04 Pin 5: nRF9160 P0.23 connects to nRF52840 P1.02

CONFIG_BOARD_PCA10090_INTERFACE1_TRACE

Pin 3: nRF9160 P0.21 connects to TRACECLK Pin 4: nRF9160 P0.22 connects to TRACEDATA0 Pin 5: nRF9160 P0.23 connects to TRACEDATA1

CONFIG_BOARD_PCA10090_INTERFACE2_COEX

Pin 6: nRF9160 COEX0 connects to COEX0_PH Pin 7: nRF9160 COEX1 connects to COEX1_PH Pin 8: nRF9160 COEX2 connects to COEX2_PH

CONFIG_BOARD_PCA10090_INTERFACE2_MCU

Pin 6: nRF9160 COEX0 connects to nRF52840 P1.13 Pin 7: nRF9160 COEX1 connects to nRF52840 P1.11 Pin 8: nRF9160 COEX2 connects to nRF52840 P1.15

CONFIG_BOARD_PCA10090_LED0_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_LED0_PHY

Route to LED on the kit

CONFIG_BOARD_PCA10090_LED1_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_LED1_PHY

Route to LED on the kit

CONFIG_BOARD_PCA10090_LED2_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_LED2_PHY

Route to LED on the kit

CONFIG_BOARD_PCA10090_LED3_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_LED3_PHY

Route to LED on the kit

CONFIG_BOARD_PCA10090_LOG_LEVEL

CONFIG_BOARD_PCA10090_LOG_LEVEL_DBG

Debug

CONFIG_BOARD_PCA10090_LOG_LEVEL_ERR

Error

CONFIG_BOARD_PCA10090_LOG_LEVEL_INF

Info

CONFIG_BOARD_PCA10090_LOG_LEVEL_OFF

Off

CONFIG_BOARD_PCA10090_LOG_LEVEL_WRN

Warning

CONFIG_BOARD_PCA10090_NRF52840_RESET

Let the nRF52840 be reset from the nRF9160 via a GPIO line. The GPIO line may only be one of the first 6 MCU interface pins. The line is active high.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_15

Pin P0.15 on nRF52840, connected to P0.19 on the nRF9160.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_17

Pin P0.17 on nRF52840, connected to P0.17 on the nRF9160.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_20

Pin P0.20 on nRF52840, connected to P0.18 on the nRF9160.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_22

Pin P0.22 on nRF52840, connected to P0.21 on the nRF9160.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P1_02

Pin P1.02 on nRF52840, connected to P0.23 on the nRF9160.

CONFIG_BOARD_PCA10090_NRF52840_RESET_P1_04

Pin P1.04 on nRF52840, connected to P0.22 on the nRF9160.

CONFIG_BOARD_PCA10090_SWITCH0_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_SWITCH0_PHY

Route to switches on the kit

CONFIG_BOARD_PCA10090_SWITCH1_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_SWITCH1_PHY

Route to switches on the kit

CONFIG_BOARD_PCA10090_UART0_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_UART0_VCOM

Route to VCOM0

CONFIG_BOARD_PCA10090_UART1_ARDUINO

Route to Arduino pins

CONFIG_BOARD_PCA10090_UART1_VCOM

Route to VCOM2

CONFIG_BOARD_PICO_PI_M4

Pico-PI iMX7D Dual

CONFIG_BOARD_QEMU_CORTEX_M0

Cortex-M0 Emulation (QEMU)

CONFIG_BOARD_QEMU_CORTEX_M3

Cortex-M3 Emulation (QEMU)

CONFIG_BOARD_QEMU_CORTEX_R5

Cortex-R5 Emulation (QEMU)

CONFIG_BOARD_QEMU_NIOS2

QEMU NIOS II target

CONFIG_BOARD_QEMU_RISCV32

QEMU RISCV32 target

CONFIG_BOARD_QEMU_RISCV64

QEMU RISCV64 target

CONFIG_BOARD_QEMU_X86

QEMU x86

CONFIG_BOARD_QEMU_X86_64

QEMU x86_64

CONFIG_BOARD_QEMU_XTENSA

Xtensa emulation using QEMU

CONFIG_BOARD_REEL_BOARD

reel board equipped with GDEH0213B1 display

CONFIG_BOARD_REEL_BOARD_V2

reel board equipped with GDEH0213B72 display

CONFIG_BOARD_RV32M1_VEGA

RV32M1 RISC-V cores

CONFIG_BOARD_SAM4S_XPLAINED

Atmel SAM4S Xplained

CONFIG_BOARD_SAM_E70_XPLAINED

Atmel SMART SAM E70 Xplained Board

CONFIG_BOARD_SELECT_SIM_EXTERNAL

Use the external SIM for communication, instead of the eSIM

CONFIG_BOARD_SENSORTILE_BOX

SensorTile.box Development Board

CONFIG_BOARD_STEVAL_FCU001V1

STM32 Flight Controller Unit

CONFIG_BOARD_STM3210C_EVAL

STM3210C-EVAL Evaluation Board

CONFIG_BOARD_STM32373C_EVAL

STM32373C_EVAL Evaluation Board

CONFIG_BOARD_STM32F030_DEMO

STM32F030 DEMO Board

CONFIG_BOARD_STM32F072B_DISCO

STM32F072B-DISCO Development Board

CONFIG_BOARD_STM32F072_EVAL

STM32F072-EVAL Development Board

CONFIG_BOARD_STM32F0_DISCO

STM32F0DISCOVERY Development Board

CONFIG_BOARD_STM32F3_DISCO

STM32F3DISCOVERY Development Board

CONFIG_BOARD_STM32F411E_DISCO

STM32F411E-DISCO Development Board

CONFIG_BOARD_STM32F412G_DISCO

STM32F412G-DISCO Development Board

CONFIG_BOARD_STM32F429I_DISC1

STM32F429I-DISC1 Development Board

CONFIG_BOARD_STM32F469I_DISCO

STM32F469I-DISCO Development Board

CONFIG_BOARD_STM32F4_DISCO

STM32F4DISCOVERY Development Board

CONFIG_BOARD_STM32F723E_DISCO

STM32F723E Discovery Development Board

CONFIG_BOARD_STM32F746G_DISCO

STM32F746G Discovery Development Board

CONFIG_BOARD_STM32F769I_DISCO

STM32F769I Discovery Development Board

CONFIG_BOARD_STM32H747I_DISCO_M4

STM32H747I Discovery Development Board

CONFIG_BOARD_STM32H747I_DISCO_M7

STM32H747I Discovery Development Board

CONFIG_BOARD_STM32L1_DISCO

STM32L1DISCOVERY Development Board

CONFIG_BOARD_STM32L476G_DISCO

STM32L476G Discovery Development Board

CONFIG_BOARD_STM32L496G_DISCO

STM32L496G Discovery Development Board

CONFIG_BOARD_STM32MP157C_DK2

STM32MP157C Discovery Development 2 Board

CONFIG_BOARD_STM32_MIN_DEV_BLACK

STM32 Minimum Development Board (Black)

CONFIG_BOARD_STM32_MIN_DEV_BLUE

STM32 Minimum Development Board (Blue)

CONFIG_BOARD_TWR_KE18F

NXP TWR-KE18F

CONFIG_BOARD_TWR_KE18F_FLEXIO_CLKOUT

Enable the CLKOUT signal on FlexIO header pin 7 (PTE10).

CONFIG_BOARD_TWR_KE18F_SPI_0_PCS2

Use PTE6 as dedicated SPI_0 PCS2 chip select

CONFIG_BOARD_TWR_KE18F_SPI_1_PCS0

Use PTD3 as dedicated SPI_1 PCS0 chip select

CONFIG_BOARD_TWR_KE18F_SPI_1_PCS2

Use PTA16 as dedicated SPI_1 PCS2 chip select

CONFIG_BOARD_TWR_KV58F220M

NXP TWR-KV58F220M

CONFIG_BOARD_UDOO_NEO_FULL_M4

UDOO Neo Full

CONFIG_BOARD_UP_SQUARED

UP Squared

CONFIG_BOARD_UP_SQUARED_ATOM

Atom E3940

CONFIG_BOARD_UP_SQUARED_CELERON

Celeron N3350

CONFIG_BOARD_UP_SQUARED_PENTIUM

Pentium N4200

CONFIG_BOARD_USB_KW24D512

NXP USB-KW24D512

CONFIG_BOARD_V2M_BEETLE

ARM V2M Beetle Board

CONFIG_BOARD_VDD_PWR_CTRL_INIT_PRIORITY

Initialization priority for the VDD power rail. Has to be greater than GPIO_NRF_INIT_PRIORITY.

CONFIG_BOARD_WARP7_M4

WaRP7 iMX7 Solo

CONFIG_BOARD_XT_SIM

Xtensa Development ISS

CONFIG_BOOTLOADER_CONTEXT_RESTORE

This option signifies that the target has a bootloader that restores CPU context upon resuming from deep sleep power state.

CONFIG_BOOTLOADER_CONTEXT_RESTORE_SUPPORTED

This option signifies that the target has options of bootloaders that support context restore upon resume from deep sleep

CONFIG_BOOTLOADER_ESP_IDF

This option will trigger the compilation of the ESP-IDF bootloader inside the build folder. At flash time, the bootloader will be flashed with the zephyr image

CONFIG_BOOTLOADER_KEXEC

This option signifies that Linux boots the kernel using kexec system call and utility. This method is used to boot the kernel over the network.

CONFIG_BOOTLOADER_MCUBOOT

This option signifies that the target uses MCUboot as a bootloader, or in other words that the image is to be chain-loaded by MCUboot. This sets several required build system and Device Tree options in order for the image generated to be bootable using the MCUboot open source bootloader. Currently this includes:

  • Setting TEXT_SECTION_OFFSET to a default value that allows space for the MCUboot image header

  • Activating SW_VECTOR_RELAY on Cortex-M0 (or Armv8-M baseline) targets with no built-in vector relocation mechanisms

  • Including dts/common/mcuboot.overlay when building the Device Tree in order to place and link the image at the slot0 offset

CONFIG_BOOTLOADER_SRAM_SIZE

This option specifies the amount of SRAM (measure in kB) reserved for a bootloader image, when either: - the Zephyr image itself is to act as the bootloader, or - Zephyr is a !XIP image, which implicitly assumes existence of a bootloader that loads the Zephyr !XIP image onto SRAM.

CONFIG_BOOT_BANNER

This option outputs a banner to the console device during boot up.

CONFIG_BOOT_DELAY

This option delays bootup for the specified amount of milliseconds. This is used to allow serial ports to get ready before starting to print information on them during boot, as some systems might boot to fast for a receiving endpoint to detect the new USB serial bus, enumerate it and get ready to receive before it actually gets data. A similar effect can be achieved by waiting for DCD on the serial port–however, not all serial ports have DCD.

CONFIG_BOOT_FLEXSPI_NAND

FlexSPI serial NAND

CONFIG_BOOT_FLEXSPI_NOR

FlexSPI serial NOR

CONFIG_BOOT_SEMC_NAND

SEMC parallel NAND

CONFIG_BOOT_SEMC_NOR

SEMC parallel NOR

CONFIG_BOOT_TIME_MEASUREMENT

This option enables the recording of timestamps during system boot.

CONFIG_BOUNDS_CHECK_BYPASS_MITIGATION

Untrusted parameters from user mode may be used in system calls to index arrays during speculative execution, also known as the Spectre V1 vulnerability. When enabled, various macros defined in misc/speculation.h will insert fence instructions or other appropriate mitigations after bounds checking any array index parameters passed in from untrusted sources (user mode threads). When disabled, these macros do nothing.

CONFIG_BT

This option enables Bluetooth support.

CONFIG_BT_A2DP

This option enables the A2DP profile

CONFIG_BT_ACL_RX_COUNT

Number of buffers available for incoming ACL data.

CONFIG_BT_ADV_SET

Maximum supported advertising sets.

CONFIG_BT_ASSERT

Use a custom Bluetooth assert implementation instead of the kernel-wide __ASSERT(), which is enabled by CONFIG_ASSERT and is disabled by default.

CONFIG_BT_ASSERT_PANIC

When CONFIG_BT_ASSERT is enabled, this option makes the code call k_panic() instead of k_oops() when an assertion is triggered.

CONFIG_BT_ASSERT_VERBOSE

When CONFIG_BT_ASSERT is enabled, this option turns on printing the cause of the assert to the console using printk().

CONFIG_BT_ATT_ENFORCE_FLOW

Enforce flow control rules on incoming PDUs, preventing a peer from sending new requests until a previous one has been responded or sending a new indication until a previous one has been confirmed. This may need to be disabled to avoid potential race conditions arising from a USB based HCI transport that splits HCI events and ACL data to separate endpoints.

CONFIG_BT_ATT_PREPARE_COUNT

Number of buffers available for ATT prepare write, setting this to 0 disables GATT long/reliable writes.

CONFIG_BT_ATT_TX_MAX

Number of ATT PDUs that can be at a single moment queued for transmission. If the application tries to send more than this amount the calls will block until an existing queued PDU gets sent.

CONFIG_BT_AUTO_PHY_UPDATE

Initiate PHY Update Procedure on connection establishment.

Disable this if you want PHY Update Procedure feature supported but want to rely on remote device to initiate the procedure at its discretion.

CONFIG_BT_AVDTP

This option enables Bluetooth AVDTP support

CONFIG_BT_BACKGROUND_SCAN_INTERVAL

Scan interval used for background scanning in 0.625 ms units

CONFIG_BT_BACKGROUND_SCAN_WINDOW

Scan window used for background scanning in 0.625 ms units

CONFIG_BT_BLUENRG_ACI

Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS.

CONFIG_BT_BONDABLE

This option enables support for Bondable Mode. In this mode, Bonding flag in AuthReq of SMP Pairing Request/Response will be set indicating the support for this mode.

CONFIG_BT_BREDR

This option enables Bluetooth BR/EDR support

CONFIG_BT_BROADCASTER

Select this for LE Broadcaster role support.

CONFIG_BT_CENTRAL

Select this for LE Central role support.

CONFIG_BT_COMPANY_ID

Set the Bluetooth Company Identifier for this device. The Linux Foundation’s Company Identifier (0x05F1) is the default value for this option although silicon vendors and hardware manufacturers can set their own. Note that the controller’s Company Identifier is controlled by BT_CTLR_COMPANY_ID. The full list of Bluetooth Company Identifiers can be found here: https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers

CONFIG_BT_CONN

CONFIG_BT_CONN_PARAM_UPDATE_TIMEOUT

The value is a timeout used by peripheral device to wait until it starts the connection parameters update procedure to change default connection parameters. The default value is set to 5s, to comply with BT protocol specification: Core 4.2 Vol 3, Part C, 9.3.12.2

CONFIG_BT_CONN_TX_MAX

Maximum number of pending TX buffers that have an associated callback. Normally this can be left to the default value, which is equal to the number of TX buffers in the stack-internal pool.

CONFIG_BT_CREATE_CONN_TIMEOUT

Timeout for pending LE Create Connection command in seconds

CONFIG_BT_CTLR

Enables support for SoC native controller implementations.

CONFIG_BT_CTLR_ADVANCED_FEATURES

Makes advanced features visible to controller developers.

CONFIG_BT_CTLR_ADV_EXT

Enable support for Bluetooth 5.0 LE Advertising Extensions in the Controller.

CONFIG_BT_CTLR_ADV_EXT_SUPPORT

CONFIG_BT_CTLR_ADV_INDICATION

Generate events indicating on air advertisement events.

CONFIG_BT_CTLR_ASSERT_HANDLER

This option enables an application-defined sink for the controller assertion mechanism. This must be defined in application code as void “bt_ctlr_assert_handle(char *, int)” and will be invoked whenever the controller code encounters an unrecoverable error.

CONFIG_BT_CTLR_CHAN_SEL_2

Enable support for Bluetooth 5.0 LE Channel Selection Algorithm #2 in the Controller.

CONFIG_BT_CTLR_CHAN_SEL_2_SUPPORT

CONFIG_BT_CTLR_COMPANY_ID

Set the Bluetooth Company Identifier that will be used in the VERSION_IND PDU. Uses BT_COMPANY_ID by default, although silicon vendors and hardware manufacturers can set their own Company Identifier for the controller. The full list of Bluetooth Company Identifiers can be found here: https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers

CONFIG_BT_CTLR_CONN_META

Enables vendor specific per-connection meta data as part of the LLL connection object.

CONFIG_BT_CTLR_CONN_PARAM_REQ

Enable support for Bluetooth v4.1 Connection Parameter Request feature in the Controller.

CONFIG_BT_CTLR_CONN_PARAM_REQ_SUPPORT

CONFIG_BT_CTLR_CONN_RSSI

Enable connection RSSI measurement.

CONFIG_BT_CTLR_CRYPTO

Use random number generation and AES encryption support functions provided by the controller.

CONFIG_BT_CTLR_DATA_LENGTH

CONFIG_BT_CTLR_DATA_LENGTH_CLEAR

Enable support for Bluetooth v4.2 LE Data Length Update procedure, up to 251 byte cleartext payloads in the Controller. Encrypted connections are not supported.

CONFIG_BT_CTLR_DATA_LENGTH_MAX

Set the maximum data length of PDU supported in the Controller.

CONFIG_BT_CTLR_DATA_LEN_UPDATE_SUPPORT

CONFIG_BT_CTLR_DEBUG_PINS

Turn on debug GPIO toggling for the BLE Controller. This is useful when debugging with a logic analyzer or profiling certain sections of the code.

CONFIG_BT_CTLR_DTM

Enable support for Direct Test Mode in the Controller.

CONFIG_BT_CTLR_DTM_HCI

Enable support for Direct Test Mode over the HCI transport.

CONFIG_BT_CTLR_DUP_FILTER_LEN

Set the number of unique BLE addresses that can be filtered as duplicates while scanning.

CONFIG_BT_CTLR_EXT_REJ_IND

Enable support for Bluetooth v4.1 Extended Reject Indication feature in the Controller.

CONFIG_BT_CTLR_EXT_REJ_IND_SUPPORT

CONFIG_BT_CTLR_EXT_SCAN_FP

Enable support for Bluetooth v4.2 LE Extended Scanner Filter Policies in the Controller.

CONFIG_BT_CTLR_EXT_SCAN_FP_SUPPORT

CONFIG_BT_CTLR_FAST_ENC

Enable connection encryption setup in 3 connection intervals. Peripheral will respond to Encryption Request with Encryption Response in the same connection interval, and also, will respond with Start Encryption Response PDU in the 3rd connection interval, hence completing encryption setup in 3 connection intervals. Encrypted data would be transmitted as fast as in 3rd connection interval from the connection establishment. Maximum CPU time in Radio ISR will increase if this feature is selected.

CONFIG_BT_CTLR_FILTER

Enable support for controller device whitelist feature

CONFIG_BT_CTLR_GPIO_LNA

Enable GPIO interface to a Low Noise Amplifier. This allows hardware designs using LNAs to let the Controller toggle their state based on radio activity.

CONFIG_BT_CTLR_GPIO_LNA_OFFSET

Time before Rx ready to turn on LNA.

CONFIG_BT_CTLR_GPIO_LNA_PIN

GPIO Pin number connected to a Low Noise Amplifier.

CONFIG_BT_CTLR_GPIO_LNA_POL_INV

Enable inverted polarity (active low) for the LNA pin.

CONFIG_BT_CTLR_GPIO_PA

Enable GPIO interface to a Power Amplifier. This allows hardware designs using PA to let the Controller toggle their state based on radio activity.

CONFIG_BT_CTLR_GPIO_PA_OFFSET

Time before Tx ready to turn on PA.

CONFIG_BT_CTLR_GPIO_PA_PIN

GPIO Pin number connected to a Power Amplifier.

CONFIG_BT_CTLR_GPIO_PA_POL_INV

Enable inverted polarity (active low) for the PA pin.

CONFIG_BT_CTLR_HCI_VS_BUILD_INFO

User-defined string that will be returned by the Zephyr VS Read Build Information command after the Zephyr version and build time. When setting this to a value different from an empty string, a space character is required at the beginning to separate it from the already included information.

CONFIG_BT_CTLR_JOB_PRIO

The interrupt priority for Ticker’s Job (SWI4) IRQ. This value shall be greater than or equal to the Ticker’s Worker IRQ priority value.

CONFIG_BT_CTLR_LE_ENC

Enable support for Bluetooth v4.0 LE Encryption feature in the Controller.

CONFIG_BT_CTLR_LE_ENC_SUPPORT

CONFIG_BT_CTLR_LE_PING

Enable support for Bluetooth v4.1 LE Ping feature in the Controller.

CONFIG_BT_CTLR_LLCP_CONN

Set the number connections for which worst-case buffer requirements for LLCP procedures must be met. Executing LLCP procedures on more than this number of connections simultaneously may cause instabilities.

CONFIG_BT_CTLR_LLID_DATA_START_EMPTY

Handle zero length L2CAP start frame.

CONFIG_BT_CTLR_LLL_PRIO

The interrupt priority for event preparation and radio IRQ.

CONFIG_BT_CTLR_LOW_LAT

Use low latency non-negotiating event preemption. This reduces Radio ISR latencies by the controller event scheduling framework. Consequently, this reduces on-air radio utilization due to redundant radio state switches.

CONFIG_BT_CTLR_LOW_LAT_ULL

Low latency ULL implementation that uses tailchaining instead of while loop to demux rx messages from LLL.

CONFIG_BT_CTLR_MESH_SCAN_FILTERS

Set the number of unique Mesh Scan Filters available as part of the Intel Mesh Vendor Specific Extensions.

CONFIG_BT_CTLR_MESH_SF_PATTERNS

Set the number of unique Mesh Scan Filter patterns available per Scan Filter as part of the Intel Mesh Vendor Specific Extensions.

CONFIG_BT_CTLR_MIN_USED_CHAN

Enable support for Bluetooth 5.0 Minimum Number of Used Channels Procedure in the Controller.

CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN

Select the nRF5 GPIOTE channel to use for PA/LNA GPIO feature.

CONFIG_BT_CTLR_PHY

CONFIG_BT_CTLR_PHY_2M

Enable support for Bluetooth 5.0 2Mbps PHY in the Controller.

CONFIG_BT_CTLR_PHY_2M_NRF

Enable support for Nordic Semiconductor proprietary 2Mbps PHY in the Controller. Encrypted connections are not supported.

CONFIG_BT_CTLR_PHY_CODED

Enable support for Bluetooth 5.0 Coded PHY in the Controller.

CONFIG_BT_CTLR_PHY_UPDATE_SUPPORT

CONFIG_BT_CTLR_PRIVACY

Enable support for Bluetooth v4.2 LE Controller-based Privacy feature in the Controller.

CONFIG_BT_CTLR_PRIVACY_SUPPORT

CONFIG_BT_CTLR_PROFILE_ISR

Turn on measurement of radio ISR latency, CPU usage and generation of controller event with these profiling data. The controller event contains current, minimum and maximum ISR entry latencies; and current, minimum and maximum ISR CPU use in micro-seconds.

CONFIG_BT_CTLR_RADIO_ENABLE_FAST

Enable use of fast radio ramp-up mode.

CONFIG_BT_CTLR_RL_SIZE

Set the size of the Resolving List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices.

CONFIG_BT_CTLR_RX_BUFFERS

Set the number of Rx PDUs to be buffered in the controller. In a 7.5ms connection interval and 2M PHY, maximum 18 packets with L2CAP payload size of 1 byte can be received.

CONFIG_BT_CTLR_RX_ENQUEUE_HOLD

Hold enqueue of Procedure Complete events with instant until after the on-air instant is reached.

CONFIG_BT_CTLR_RX_PDU_META

Enable RX pdu meta data

CONFIG_BT_CTLR_RX_PRIO

CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE

High priority Rx thread stack size

CONFIG_BT_CTLR_SCAN_INDICATION

Generate events indicating on air scanner events.

CONFIG_BT_CTLR_SCAN_REQ_NOTIFY

Generate events notifying the on air scan requests received.

CONFIG_BT_CTLR_SCAN_REQ_RSSI

Measure RSSI of the on air scan requests received.

CONFIG_BT_CTLR_SCHED_ADVANCED

Enable non-overlapping placement of observer, initiator and master roles in timespace. Uses window offset in connection updates and uses connection parameter request in slave role to negotiate non-overlapping placement with active master roles to avoid slave roles drifting into active master roles in the local controller.

This feature maximizes the average data transmission amongst active concurrent master and slave connections while other observer, initiator, master or slave roles are active in the local controller.

Disabling this feature will lead to overlapping role in timespace leading to skipped events amongst active roles.

CONFIG_BT_CTLR_SCHED_ADVANCED_SUPPORT

CONFIG_BT_CTLR_SETTINGS

Enable use of settings system in controller.

CONFIG_BT_CTLR_SLAVE_FEAT_REQ

Enable support for Bluetooth v4.1 Slave-initiated Features Exchange feature in the Controller.

CONFIG_BT_CTLR_SLAVE_FEAT_REQ_SUPPORT

CONFIG_BT_CTLR_SUBVERSION_NUMBER

Set the Subversion Number that will be used in VERSION_IND PDU.

CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER

Implement the tIFS Trx SW switch with the same TIMER instance, as the one used for BLE event timing. Requires SW switching be enabled. Using a single TIMER: (+) frees up one TIMER instance (+) removes jitter for HCTO implementation (-) introduces drifting to the absolute time inside BLE events, that increases linearly with the number of packets exchanged in the event (-) makes it impossible to use most of the pre-programmed PPI channels for the controller, resulting in 4 channels less left for other uses

CONFIG_BT_CTLR_TIFS_HW

Enable use of hardware accelerated tIFS Trx switching.

CONFIG_BT_CTLR_TIFS_HW_SUPPORT

CONFIG_BT_CTLR_TO_HOST_UART_DEV_NAME

This option specifies the name of UART device to be used to connect to an external Bluetooth Host when Zephyr is acting as a Bluetooth Controller.

CONFIG_BT_CTLR_TX_BUFFERS

Set the number of Tx PDUs to be queued for transmission in the controller. In a 7.5ms connection interval and 2M PHY, maximum 19 packets can be enqueued, with 18 packets with L2CAP payload size of 1 byte can be acknowledged.

CONFIG_BT_CTLR_TX_BUFFER_SIZE

Size of the Tx buffers and the value returned in HCI LE Read Buffer Size command response. If this size if greater than effective PDU size then controller will perform fragmentation before transmitting on the the packet on air. Maximum is set to 16384 due to implementation limitations (use of u16_t for size/length variables).

CONFIG_BT_CTLR_TX_PWR_0

0 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_12

-12 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_16

-16 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_20

-20 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_30

-30 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_4

-4 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_40

-40 dBm

CONFIG_BT_CTLR_TX_PWR_MINUS_8

-8 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_2

+2 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_3

+3 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_4

+4 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_5

+5 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_6

+6 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_7

+7 dBm

CONFIG_BT_CTLR_TX_PWR_PLUS_8

+8 dBm

CONFIG_BT_CTLR_TX_RETRY_DISABLE

Avoid retransmission of a PDU if peer device Nack-ed a transmission in the current connection event, close the connection event so as to save current consumption on retries (in case peer has no buffers to receive new PDUs).

Enabling this will lower power consumption, but increase transmission latencies by one connection interval as the next attempt to send a PDU would happen in the next connection event instead of repeated retries in the current connection event.

CONFIG_BT_CTLR_ULL_HIGH_PRIO

The interrupt priority for Ticker’s Worker IRQ and Upper Link Layer higher priority functions.

CONFIG_BT_CTLR_ULL_LOW_PRIO

The interrupt priority for Ticker’s Job IRQ and Upper Link Layer lower priority functions.

CONFIG_BT_CTLR_USER_EVT_RANGE

Number of event types reserved for proprietary use. The range is typically used when BT_CTLR_USER_EXT is in use.

CONFIG_BT_CTLR_USER_EXT

Catch-all for enabling proprietary event types in Controller behavior.

CONFIG_BT_CTLR_VERSION_SETTINGS

Make the controller’s Company Id and Subversion Number configurable through settings system.

CONFIG_BT_CTLR_WORKER_PRIO

The interrupt priority for event preparation and radio IRQ. This value shall be less than or equal to the Ticker’s Job priority value.

CONFIG_BT_CTLR_XTAL_ADVANCED

Enables advanced event preparation offset ahead of radio tx/rx, taking into account predictive processing time requirements in preparation to the event, like control procedure handling and CPU execution speeds. Crystal oscillator is retained between closely spaced consecutive radio events to reduce the overall number of crystal settling current consumptions.

This feature maximizes radio utilization in an average role event timeslice when they are closely spaced by using a reduced offset between preparation and radio event.

By disabling this feature, the controller will use a constant offset between the preparation and radio event. The controller will toggle crystal oscillator between two closely spaced radio events leading to higher average current due to increased number of crystal settling current consumptions.

CONFIG_BT_CTLR_XTAL_ADVANCED_SUPPORT

CONFIG_BT_CTLR_XTAL_THRESHOLD

Configure the optimal delta in micro seconds between two consecutive radio events, event done to next preparation, below which (active clock) crystal will be retained. This value is board dependent.

CONFIG_BT_CTLR_ZLI

Enable support for use of Zero Latency IRQ feature. Note, applications shall not use Zero Latency IRQ themselves when this option is selected, else will impact controller stability.

CONFIG_BT_CUSTOM

Select a custom, non-HCI based stack. If you’re not sure what this is, you probably want the HCI-based stack instead.

CONFIG_BT_DATA_LEN_UPDATE

Enable support for Bluetooth v4.2 LE Data Length Update procedure.

CONFIG_BT_DEBUG

CONFIG_BT_DEBUG_A2DP

This option enables debug support for the Bluetooth A2DP profile.

CONFIG_BT_DEBUG_ATT

This option enables debug support for the Bluetooth Attribute Protocol (ATT).

CONFIG_BT_DEBUG_AVDTP

This option enables debug support for the Bluetooth AVDTP.

CONFIG_BT_DEBUG_CONN

This option enables debug support for Bluetooth connection handling.

CONFIG_BT_DEBUG_GATT

This option enables debug support for the Bluetooth Generic Attribute Profile (GATT).

CONFIG_BT_DEBUG_HCI_CORE

This option enables debug support for Bluetooth HCI core.

CONFIG_BT_DEBUG_HCI_DRIVER

This option enables debug support for the active Bluetooth HCI driver, including the Controller-side HCI layer when included in the build.

CONFIG_BT_DEBUG_HFP_HF

This option enables debug support for the Bluetooth Hands Free Profile (HFP).

CONFIG_BT_DEBUG_KEYS

This option enables debug support for the handling of Bluetooth security keys.

CONFIG_BT_DEBUG_L2CAP

This option enables debug support for the Bluetooth L2ACP layer.

CONFIG_BT_DEBUG_LOG

This option enables Bluetooth debug going to standard serial console.

CONFIG_BT_DEBUG_MONITOR

Use a custom logging protocol over the console UART instead of plain-text output. Requires a special application on the host side that can decode this protocol. Currently the ‘btmon’ tool from BlueZ is capable of doing this.

If the target board has two or more external UARTs it is possible to keep using UART_CONSOLE together with this option, however if there is only a single external UART then UART_CONSOLE needs to be disabled (in which case printk/printf will get encoded into the monitor protocol).

CONFIG_BT_DEBUG_NONE

Select this to disable all Bluetooth debug logs.

CONFIG_BT_DEBUG_RFCOMM

This option enables debug support for the Bluetooth RFCOMM layer.

CONFIG_BT_DEBUG_RPA

This option enables debug support for the Bluetooth Resolvable Private Address (RPA) generation and resolution.

CONFIG_BT_DEBUG_SDP

This option enables debug support for the Bluetooth Service Discovery Protocol (SDP).

CONFIG_BT_DEBUG_SERVICE

This option enables debug support for the Bluetooth Services.

CONFIG_BT_DEBUG_SETTINGS

This option enables debug support for Bluetooth storage.

CONFIG_BT_DEBUG_SMP

This option enables debug support for the Bluetooth Security Manager Protocol (SMP).

CONFIG_BT_DEVICE_APPEARANCE

Bluetooth device appearance. For the list of possible values please consult the following link: https://www.bluetooth.com/specifications/assigned-numbers

CONFIG_BT_DEVICE_NAME

Bluetooth device name. Name can be up to 248 bytes long (excluding NULL termination). Can be empty string.

CONFIG_BT_DEVICE_NAME_DYNAMIC

Enabling this option allows for runtime configuration of Bluetooth device name.

CONFIG_BT_DEVICE_NAME_GATT_WRITABLE

Enabling this option allows remote GATT clients to write to device name GAP characteristic.

CONFIG_BT_DEVICE_NAME_MAX

Bluetooth device name storage size. Storage can be up to 248 bytes long (excluding NULL termination).

CONFIG_BT_DISCARDABLE_BUF_COUNT

Number of buffers in a separate buffer pool for events which the HCI driver considers discardable. Examples of such events could be e.g. Advertising Reports. The benefit of having such a pool means that the if there is a heavy inflow of such events it will not cause the allocation for other critical events to block and may even eliminate deadlocks in some cases.

CONFIG_BT_ECC

This option adds support for ECDH HCI commands.

CONFIG_BT_FIXED_PASSKEY

With this option enabled, the application will be able to call the bt_passkey_set() API to set a fixed passkey. If set, the pairing_confim() callback will be called for all incoming pairings.

CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS

This allows to configure peripheral preferred connection parameters. Enabling this option results in adding PPCP characteristic in GAP and sending request for connection parameters update after GAP recommended 5 seconds of connection as peripheral. If disabled it is up to application to set expected connection parameters.

CONFIG_BT_GATT_BAS

Enable GATT Battery service

CONFIG_BT_GATT_BAS_LOG_LEVEL

Sets log level for the Battery service. Levels are: 0 OFF, do not write 1 ERROR, only write LOG_ERR 2 WARNING, write LOG_WRN in addition to previous level 3 INFO, write LOG_INF in addition to previous levels 4 DEBUG, write LOG_DBG in addition to previous levels

CONFIG_BT_GATT_CACHING

This option enables support for GATT Caching. When enabled the stack will register Client Supported Features and Database Hash characteristics which can be used by clients to detect if anything has changed on the GATT database.

CONFIG_BT_GATT_CLIENT

This option enables support for the GATT Client role.

CONFIG_BT_GATT_DIS

Enable GATT Device Information service

CONFIG_BT_GATT_DIS_FW_REV

Enable Firmware Revision characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_FW_REV_STR

Enable firmware revision characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_HW_REV

Enable Hardware Revision characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_HW_REV_STR

Enable hardware revision characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_MANUF

The device manufacturer inside Device Information Service.

CONFIG_BT_GATT_DIS_MODEL

The device model inside Device Information Service.

CONFIG_BT_GATT_DIS_PNP

Enable PnP_ID characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_PNP_PID

The Product ID field is intended to distinguish between different products made by the vendor identified with the Vendor ID field. The vendors themselves manage Product ID field values.

CONFIG_BT_GATT_DIS_PNP_VER

The Product Version field is a numeric expression identifying the device release number in Binary-Coded Decimal. This is a vendor-assigned value, which defines the version of the product identified by the Vendor ID and Product ID fields. This field is intended to differentiate between versions of products with identical Vendor IDs and Product IDs. The value of the field value is 0xJJMN for version JJ.M.N (JJ - major version number, M - minor version number, N - sub-minor version number); e.g., version 2.1.3 is represented with value 0x0213 and version 2.0.0 is represented with a value of 0x0200. When upward-compatible changes are made to the device, it is recommended that the minor version number be incremented. If incompatible changes are made to the device, it is recommended that the major version number be incremented. The sub-minor version is incremented for bug fixes.

CONFIG_BT_GATT_DIS_PNP_VID

The Vendor ID field is intended to uniquely identify the vendor of the device. This field is used in conjunction with Vendor ID Source field, which determines which organization assigned the Vendor ID field value. Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID, and the USB Implementers Forum assigns Vendor IDs, either of which can be used for the Vendor ID field value. Device providers should procure the Vendor ID from the USB Implementers Forum or the Company Identifier from the Bluetooth SIG.

CONFIG_BT_GATT_DIS_PNP_VID_SRC

The Vendor ID Source field designates which organization assigned the value used in the Vendor ID field value. The possible values are: - 1 Bluetooth SIG, the Vendor ID was assigned by the Bluetooth SIG - 2 USB IF, the Vendor ID was assigned by the USB IF

CONFIG_BT_GATT_DIS_SERIAL_NUMBER

Enable Serial Number characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_SERIAL_NUMBER_STR

Enable Serial Number characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_SETTINGS

Enable Settings usage in Device Information Service.

CONFIG_BT_GATT_DIS_STR_MAX

Bluetooth DIS string storage size. Storage can be up to 248 bytes long (excluding NULL termination).

CONFIG_BT_GATT_DIS_SW_REV

Enable Software Revision characteristic in Device Information Service.

CONFIG_BT_GATT_DIS_SW_REV_STR

Enable software revision characteristic in Device Information Service.

CONFIG_BT_GATT_DYNAMIC_DB

This option enables registering/unregistering services at runtime.

CONFIG_BT_GATT_ENFORCE_CHANGE_UNAWARE

When enable this option blocks notification and indications to client to conform to the following statement from the Bluetooth 5.1 specification: ‘…the server shall not send notifications and indications to such a client until it becomes change-aware.” In case the service cannot deal with sudden errors (-EAGAIN) then it shall not use this option.

CONFIG_BT_GATT_HRS

Enable GATT Heart Rate service

CONFIG_BT_GATT_HRS_LOG_LEVEL

Sets log level for the Heart Rate service. Levels are: 0 OFF, do not write 1 ERROR, only write LOG_ERR 2 WARNING, write LOG_WRN in addition to previous level 3 INFO, write LOG_INF in addition to previous levels 4 DEBUG, write LOG_DBG in addition to previous levels

CONFIG_BT_GATT_READ_MULTIPLE

This option enables support for the GATT Read Multiple Characteristic Values procedure.

CONFIG_BT_GATT_SERVICE_CHANGED

This option enables support for the service changed characteristic.

CONFIG_BT_H4

Bluetooth H:4 UART driver. Requires hardware flow control lines to be available.

CONFIG_BT_H5

Bluetooth three-wire (H:5) UART driver. Implementation of HCI Three-Wire UART Transport Layer.

CONFIG_BT_HAS_HCI_VS

This option is set by the Bluetooth controller to indicate support for the Zephyr HCI Vendor-Specific Commands and Event.

CONFIG_BT_HCI

HCI-based stack with optional host & controller parts and an HCI driver in between.

CONFIG_BT_HCI_ACL_FLOW_CONTROL

Enable support for throttling ACL buffers from the controller to the host. This is particularly useful when the host and controller are on separate cores since it ensures that we do not run out of incoming ACL buffers.

CONFIG_BT_HCI_CMD_COUNT

Number of buffers available for HCI commands.

CONFIG_BT_HCI_ECC_STACK_SIZE

NOTE: This is an advanced setting and should not be changed unless absolutely necessary

CONFIG_BT_HCI_HOST

CONFIG_BT_HCI_MESH_EXT

Enable support for the Bluetooth Mesh HCI Commands.

CONFIG_BT_HCI_RAW

This option allows to access Bluetooth controller from the application with the RAW HCI protocol.

CONFIG_BT_HCI_RAW_RESERVE

This option is used by the HCI raw transport implementation to declare how much headroom it needs for any HCI transport headers.

CONFIG_BT_HCI_RESERVE

Headroom that the driver needs for sending and receiving buffers. Add a new ‘default’ entry for each new driver.

CONFIG_BT_HCI_TX_PRIO

CONFIG_BT_HCI_TX_STACK_SIZE

Stack size needed for executing bt_send with specified driver. NOTE: This is an advanced setting and should not be changed unless absolutely necessary

CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT

Override HCI Tx thread stack size

CONFIG_BT_HCI_VS

Enable support for the Zephyr HCI Vendor-Specific Commands in the Host and/or Controller. This enables Set Version Information, Supported Commands, Supported Features vendor commands.

CONFIG_BT_HCI_VS_EVT_USER

Enable registering a callback for delegating to the user the handling of VS events that are not known to the stack

CONFIG_BT_HCI_VS_EXT

Enable support for the Zephyr HCI Vendor-Specific Extensions in the Host and/or Controller. This enables Write BD_ADDR, Read Build Info, Read Static Addresses and Read Key Hierarchy Roots vendor commands.

CONFIG_BT_HCI_VS_EXT_DETECT

Use some heuristics to try to guess in advance whether the controller supports the HCI vendor extensions in advance, in order to prevent sending vendor commands to controller which may interpret them in completely different ways.

CONFIG_BT_HFP_HF

This option enables Bluetooth HF support

CONFIG_BT_HOST_CRYPTO

CONFIG_BT_ID_MAX

Maximum number of supported local identity addresses. For most products this is safe to leave as the default value (1).

CONFIG_BT_KEYS_OVERWRITE_OLDEST

With this option enabled, if a pairing attempt occurs and the key storage is full, then the oldest keys in storage will be removed to free space for the new pairing keys.

CONFIG_BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING

With this option enabled, aging counter will be stored in settings every time a successful pairing occurs. This increases flash wear out but offers a more correct finding of the oldest unused pairing info.

CONFIG_BT_L2CAP_DYNAMIC_CHANNEL

This option enables support for LE Connection oriented Channels, allowing the creation of dynamic L2CAP Channels.

CONFIG_BT_L2CAP_RX_MTU

Maximum size of each incoming L2CAP PDU.

CONFIG_BT_L2CAP_TX_BUF_COUNT

Number of buffers available for outgoing L2CAP packets.

CONFIG_BT_L2CAP_TX_FRAG_COUNT

Number of buffers available for fragments of TX buffers. Warning: setting this to 0 means that the application must ensure that queued TX buffers never need to be fragmented, i.e. that the controller’s buffer size is large enough. If this is not ensured, and there are no dedicated fragment buffers, a deadlock may occur. In most cases the default value of 2 is a safe bet.

CONFIG_BT_L2CAP_TX_MTU

Maximum L2CAP MTU for L2CAP TX buffers.

CONFIG_BT_LLL_VENDOR_NORDIC

Use Nordic Lower Link Layer implementation.

CONFIG_BT_LLL_VENDOR_OPENISA

Use OpenISA Lower Link Layer implementation.

CONFIG_BT_LL_SW_LEGACY

Use Zephyr software BLE Link Layer implementation.

CONFIG_BT_LL_SW_SPLIT

Use Zephyr software BLE Link Layer ULL LLL split implementation.

CONFIG_BT_LOG_LEVEL

CONFIG_BT_LOG_LEVEL_DBG

Debug

CONFIG_BT_LOG_LEVEL_ERR

Error

CONFIG_BT_LOG_LEVEL_INF

Info

CONFIG_BT_LOG_LEVEL_OFF

Off

CONFIG_BT_LOG_LEVEL_WRN

Warning

CONFIG_BT_MAX_CONN

Maximum number of simultaneous Bluetooth connections supported.

CONFIG_BT_MAX_PAIRED

Maximum number of paired Bluetooth devices. The minimum (and default) number is 1.

CONFIG_BT_MAX_SCO_CONN

Maximum number of simultaneous Bluetooth synchronous connections supported. The minimum (and default) number is 1.

CONFIG_BT_MAYFLY_YIELD_AFTER_CALL

Only process one mayfly callback per invocation (legacy behavior). If set to ‘n’, all pending mayflies for callee are executed before yielding

CONFIG_BT_MESH

This option enables Bluetooth Mesh support. The specific features that are available may depend on other features that have been enabled in the stack, such as GATT support.

CONFIG_BT_MESH_ADV_BUF_COUNT

Number of advertising buffers available. This should be chosen based on what kind of features the local node should have. E.g. a relay will perform better the more buffers it has. Another thing to consider is outgoing segmented messages. There must be at least three more advertising buffers than the maximum supported outgoing segment count (BT_MESH_TX_SEG_MAX).

CONFIG_BT_MESH_APP_KEY_COUNT

This option specifies how many application keys the device can store per network.

CONFIG_BT_MESH_CFG_CLI

Enable support for the configuration client model.

CONFIG_BT_MESH_CRPL

This options specifies the maximum capacity of the replay protection list. This option is similar to the network message cache size, but has a different purpose.

CONFIG_BT_MESH_DEBUG

Use this option to enable debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_ACCESS

Use this option to enable Access layer and device composition related debug logs for Bluetooth Mesh.

CONFIG_BT_MESH_DEBUG_ADV

Use this option to enable advertising debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_BEACON

Use this option to enable Beacon-related debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_CRYPTO

Use this option to enable cryptographic debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_FRIEND

Use this option to enable Friend debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_LOW_POWER

Use this option to enable Low Power debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_MODEL

Use this option to enable debug logs for the Foundation Models.

CONFIG_BT_MESH_DEBUG_NET

Use this option to enable Network layer debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_PROV

Use this option to enable Provisioning debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_PROXY

Use this option to enable Proxy protocol debug logs.

CONFIG_BT_MESH_DEBUG_SETTINGS

Use this option to enable persistent settings debug logs.

CONFIG_BT_MESH_DEBUG_TRANS

Use this option to enable Transport layer debug logs for the Bluetooth Mesh functionality.

CONFIG_BT_MESH_DEBUG_USE_ID_ADDR

This option forces the usage of the local identity address for all advertising. This can be a help for debugging (analyzing traces), however it should never be enabled for a production build as it compromises the privacy of the device.

CONFIG_BT_MESH_FRIEND

Enable this option to be able to act as a Friend Node.

CONFIG_BT_MESH_FRIEND_LPN_COUNT

Number of Low Power Nodes the Friend can have a Friendship with simultaneously.

CONFIG_BT_MESH_FRIEND_QUEUE_SIZE

Minimum number of buffers available to be stored for each local Friend Queue.

CONFIG_BT_MESH_FRIEND_RECV_WIN

Receive Window in milliseconds supported by the Friend node.

CONFIG_BT_MESH_FRIEND_SEG_RX

Number of incomplete segment lists that we track for each LPN that we are Friends for. In other words, this determines how many elements we can simultaneously be receiving segmented messages from when the messages are going into the Friend queue.

CONFIG_BT_MESH_FRIEND_SUB_LIST_SIZE

Size of the Subscription List that can be supported by a Friend node for a Low Power node.

CONFIG_BT_MESH_GATT_PROXY

This option enables support for the Mesh GATT Proxy Service, i.e. the ability to act as a proxy between a Mesh GATT Client and a Mesh network.

CONFIG_BT_MESH_HEALTH_CLI

Enable support for the health client model.

CONFIG_BT_MESH_IVU_DIVIDER

When the IV Update state enters Normal operation or IV Update in Progress, we need to keep track of how many hours has passed in the state, since the specification requires us to remain in the state at least for 96 hours (Update in Progress has an additional upper limit of 144 hours).

In order to fulfill the above requirement, even if the node might be powered off once in a while, we need to store persistently how many hours the node has been in the state. This doesn’t necessarily need to happen every hour (thanks to the flexible duration range). The exact cadence will depend a lot on the ways that the node will be used and what kind of power source it has.

Since there is no single optimal answer, this configuration option allows specifying a divider, i.e. how many intervals the 96 hour minimum gets split into. After each interval the duration that the node has been in the current state gets stored to flash. E.g. the default value of 4 means that the state is saved every 24 hours (96 / 4).

CONFIG_BT_MESH_IV_UPDATE_TEST

This option removes the 96 hour limit of the IV Update Procedure and lets the state be changed at any time.

CONFIG_BT_MESH_LABEL_COUNT

This option specifies how many Label UUIDs can be stored.

CONFIG_BT_MESH_LOW_POWER

Enable this option to be able to act as a Low Power Node.

CONFIG_BT_MESH_LPN_AUTO

Automatically enable LPN functionality once provisioned and start looking for Friend nodes. If this option is disabled LPN mode needs to be manually enabled by calling bt_mesh_lpn_set(true).

CONFIG_BT_MESH_LPN_AUTO_TIMEOUT

Time in seconds from the last received message, that the node will wait before starting to look for Friend nodes.

CONFIG_BT_MESH_LPN_ESTABLISHMENT

Perform the Friendship establishment using low power, with the help of a reduced scan duty cycle. The downside of this is that the node may miss out on messages intended for it until it has successfully set up Friendship with a Friend node.

CONFIG_BT_MESH_LPN_GROUPS

Maximum number of groups that the LPN can subscribe to.

CONFIG_BT_MESH_LPN_INIT_POLL_TIMEOUT

The initial value of the PollTimeout timer when Friendship gets established for the first time. After this the timeout will gradually grow toward the actual PollTimeout, doubling in value for each iteration. The value is in units of 100 milliseconds, so e.g. a value of 300 means 30 seconds.

CONFIG_BT_MESH_LPN_MIN_QUEUE_SIZE

The MinQueueSizeLog field is defined as log_2(N), where N is the minimum number of maximum size Lower Transport PDUs that the Friend node can store in its Friend Queue. As an example, MinQueueSizeLog value 1 gives N = 2, and value 7 gives N = 128.

CONFIG_BT_MESH_LPN_POLL_TIMEOUT

PollTimeout timer is used to measure time between two consecutive requests sent by the Low Power node. If no requests are received by the Friend node before the PollTimeout timer expires, then the friendship is considered terminated. The value is in units of 100 milliseconds, so e.g. a value of 300 means 30 seconds.

CONFIG_BT_MESH_LPN_RECV_DELAY

The ReceiveDelay is the time between the Low Power node sending a request and listening for a response. This delay allows the Friend node time to prepare the response. The value is in units of milliseconds.

CONFIG_BT_MESH_LPN_RECV_WIN_FACTOR

The contribution of the supported Receive Window used in Friend Offer Delay calculations. 0 = 1, 1 = 1.5, 2 = 2, 3 = 2.5.

CONFIG_BT_MESH_LPN_RETRY_TIMEOUT

Time in seconds between Friend Requests, if a previous Friend Request did not receive any acceptable Friend Offers.

CONFIG_BT_MESH_LPN_RSSI_FACTOR

The contribution of the RSSI measured by the Friend node used in Friend Offer Delay calculations. 0 = 1, 1 = 1.5, 2 = 2, 3 = 2.5.

CONFIG_BT_MESH_LPN_SCAN_LATENCY

Latency in milliseconds that it takes to enable scanning. This is in practice how much time in advance before the Receive Window that scanning is requested to be enabled.

CONFIG_BT_MESH_MODEL_EXTENSIONS

Enable support for the model extension concept, allowing the Access layer to know about Mesh model relationships.

CONFIG_BT_MESH_MODEL_GROUP_COUNT

This option specifies how many group addresses each model can at most be subscribed to.

CONFIG_BT_MESH_MODEL_KEY_COUNT

This option specifies how many application keys each model can at most be bound to.

CONFIG_BT_MESH_MSG_CACHE_SIZE

Number of messages that are cached for the network. This helps prevent unnecessary decryption operations and unnecessary relays. This option is similar to the replay protection list, but has a different purpose.

CONFIG_BT_MESH_NODE_COUNT

This option specifies how many nodes each network can at most save in the provisioning database.

CONFIG_BT_MESH_NODE_ID_TIMEOUT

This option determines for how long the local node advertises using Node Identity. The given value is in seconds. The specification limits this to 60 seconds, and implies that to be the appropriate value as well, so just leaving this as the default is the safest option.

CONFIG_BT_MESH_PB_ADV

Enable this option to allow the device to be provisioned over the advertising bearer.

CONFIG_BT_MESH_PB_GATT

Enable this option to allow the device to be provisioned over GATT.

CONFIG_BT_MESH_PROV

CONFIG_BT_MESH_PROVISIONER

Enable this option to have support for provisioning remote devices.

CONFIG_BT_MESH_PROXY

CONFIG_BT_MESH_PROXY_FILTER_SIZE

This option specifies how many Proxy Filter entries the local node supports.

CONFIG_BT_MESH_RELAY

Support for acting as a Mesh Relay Node.

CONFIG_BT_MESH_RPL_STORE_TIMEOUT

This value defines in seconds how soon the RPL gets written to persistent storage after a change occurs. If the node receives messages frequently it may make sense to have this set to a large value, whereas if the RPL gets updated infrequently a value as low as 0 (write immediately) may make sense. Note that if the node operates a security sensitive use case, and there’s a risk of sudden power loss, it may be a security vulnerability to set this value to anything else than 0 (a power loss before writing to storage exposes the node to potential message replay attacks).

CONFIG_BT_MESH_RX_SDU_MAX

Maximum incoming Upper Transport Access PDU length. This determines also how many segments incoming segmented messages can have. Each segment can contain 12 bytes, so this value should be set to a multiple of 12 to avoid wasted memory. The minimum requirement is 2 segments (24 bytes) whereas the maximum supported by the Mesh specification is 32 segments (384 bytes).

CONFIG_BT_MESH_RX_SEG_MSG_COUNT

Maximum number of simultaneous incoming multi-segment and/or reliable messages.

CONFIG_BT_MESH_SELF_TEST

This option adds extra self-tests which are run every time mesh networking is initialized.

CONFIG_BT_MESH_SEQ_STORE_RATE

This value defines how often the local sequence number gets updated in persistent storage (i.e. flash). E.g. a value of 100 means that the sequence number will be stored to flash on every 100th increment. If the node sends messages very frequently a higher value makes more sense, whereas if the node sends infrequently a value as low as 0 (update storage for every increment) can make sense. When the stack gets initialized it will add this number to the last stored one, so that it starts off with a value that’s guaranteed to be larger than the last one used before power off.

CONFIG_BT_MESH_SHELL

Activate shell module that provides Bluetooth Mesh commands to the console.

CONFIG_BT_MESH_STORE_TIMEOUT

This value defines in seconds how soon any pending changes are actually written into persistent storage (flash) after a change occurs.

CONFIG_BT_MESH_SUBNET_COUNT

This option specifies how many subnets a Mesh network can participate in at the same time.

CONFIG_BT_MESH_TX_SEG_MAX

Maximum number of segments supported for outgoing messages. This value should typically be fine-tuned based on what models the local node supports, i.e. what’s the largest message payload that the node needs to be able to send. This value affects memory and call stack consumption, which is why the default is lower than the maximum that the specification would allow (32 segments).

The maximum outgoing SDU size is 12 times this number (out of which 4 or 8 bytes is used for the Transport Layer MIC). For example, 5 segments means the maximum SDU size is 60 bytes, which leaves 56 bytes for application layer data using a 4-byte MIC and 52 bytes using an 8-byte MIC.

Be sure to specify a sufficient number of advertising buffers when setting this option to a higher value. There must be at least three more advertising buffers (BT_MESH_ADV_BUF_COUNT) as there are outgoing segments.

CONFIG_BT_MESH_TX_SEG_MSG_COUNT

Maximum number of simultaneous outgoing multi-segment and/or reliable messages.

CONFIG_BT_MONITOR_ON_DEV_NAME

This option specifies the name of UART device to be used for the Bluetooth monitor logging.

CONFIG_BT_NO_DRIVER

This is intended for unit tests where no internal driver should be selected.

CONFIG_BT_OBSERVER

Select this for LE Observer role support.

CONFIG_BT_OOB_DATA_FIXED

With this option enabled, the application will be able to perform LESC pairing with OOB data that consists of fixed random number and confirm value. This option should only be enabled for debugging and should never be used in production.

CONFIG_BT_PAGE_TIMEOUT

This option sets the page timeout value. Value is selected as (N * 0.625) ms.

CONFIG_BT_PERIPHERAL

Select this for LE Peripheral role support.

CONFIG_BT_PERIPHERAL_PREF_MAX_INT

Range 3200 to 65534 is invalid. 65535 represents no specific value.

CONFIG_BT_PERIPHERAL_PREF_MIN_INT

Range 3200 to 65534 is invalid. 65535 represents no specific value.

CONFIG_BT_PERIPHERAL_PREF_SLAVE_LATENCY

Peripheral preferred slave latency in Connection Intervals

CONFIG_BT_PERIPHERAL_PREF_TIMEOUT

It is up to user to provide valid timeout which pass required minimum value: in milliseconds it shall be larger than “(1+ Conn_Latency) * Conn_Interval_Max * 2” where Conn_Interval_Max is given in milliseconds. Range 3200 to 65534 is invalid. 65535 represents no specific value.

CONFIG_BT_PHY_UPDATE

Enable support for Bluetooth 5.0 PHY Update Procedure.

CONFIG_BT_PRIVACY

Enable local Privacy Feature support. This makes it possible to use Resolvable Private Addresses (RPAs).

CONFIG_BT_RECV_IS_RX_THREAD

CONFIG_BT_REMOTE_VERSION

Enable this to get access to the remote version in the Controller and in the Host through bt_conn_get_info(). The fields in question can be then found in the bt_conn_info struct.

CONFIG_BT_RFCOMM

This option enables Bluetooth RFCOMM support

CONFIG_BT_RFCOMM_L2CAP_MTU

Maximum size of L2CAP PDU for RFCOMM frames.

CONFIG_BT_RPA

CONFIG_BT_RPA_TIMEOUT

This option defines how often resolvable private address is rotated. Value is provided in seconds and defaults to 900 seconds (15 minutes).

CONFIG_BT_RPMSG

Bluetooth HCI driver for communication with another CPU using RPMsg framework.

CONFIG_BT_RPMSG_NRF53

Enable RPMsg configuration for nRF53. Two channels of the IPM driver are used in the HCI driver: channel 0 for TX and channel 1 for RX.

CONFIG_BT_RPMSG_NRF53_RX_PRIO

RPMsg RX thread priority

CONFIG_BT_RPMSG_NRF53_RX_STACK_SIZE

RPMsg stack size for RX thread

CONFIG_BT_RX_BUF_COUNT

Number of buffers available for incoming ACL packets or HCI events from the controller.

CONFIG_BT_RX_BUF_LEN

Maximum data size for each HCI RX buffer. This size includes everything starting with the ACL or HCI event headers. Note that buffer sizes are always rounded up to the nearest multiple of 4, so if this Kconfig value is something else then there will be some wasted space. The minimum of 73 has been taken for LE SC which has an L2CAP MTU of 65 bytes. On top of this there’s the L2CAP header (4 bytes) and the ACL header (also 4 bytes) which yields 73 bytes.

CONFIG_BT_RX_PRIO

CONFIG_BT_RX_STACK_SIZE

Size of the receiving thread stack. This is the context from which all event callbacks to the application occur. The default value is sufficient for basic operation, but if the application needs to do advanced things in its callbacks that require extra stack space, this value can be increased to accommodate for that.

CONFIG_BT_RX_USER_PDU_LEN

Maximum data size for each proprietary PDU. This size includes link layer header and payload. It does not account for HCI event headers as these PDUs are assumed to not go across HCI.

CONFIG_BT_SCAN_WITH_IDENTITY

Enable this if you want to perform active scanning using the local identity address as the scanner address. By default the stack will always use a non-resolvable private address (NRPA) in order to avoid disclosing local identity information. However, if the use case requires disclosing it then enable this option.

CONFIG_BT_SETTINGS

When selected, the Bluetooth stack will take care of storing (and restoring) the Bluetooth state (e.g. pairing keys) and configuration persistently in flash.

When this option has been enabled, it’s important that the application makes a call to settings_load() after having done all necessary initialization (e.g. calling bt_enable). The reason settings_load() is handled externally to the stack, is that there may be other subsystems using the settings API, in which case it’s more efficient to load all settings in one go, instead of each subsystem doing it independently.

CONFIG_BT_SETTINGS_CCC_LAZY_LOADING

Load Client Configuration Characteristic setting right after a bonded device connects. Disabling this option will increase memory usage as CCC values for all bonded devices will be loaded when calling settings_load.

CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE

Store Client Configuration Characteristic value right after it has been updated.

By default, CCC is only stored on disconnection. Choosing this option is safer for battery-powered devices or devices that expect to be reset suddenly. However, it requires additional workqueue stack space.

CONFIG_BT_SETTINGS_USE_PRINTK

When selected, Bluetooth settings will use snprintk to encode key strings. When not selected, Bluetooth settings will use a faster builtin function to encode the key string. The drawback is that if printk is enabled then the program memory footprint will be larger.

CONFIG_BT_SHELL

Activate shell module that provides Bluetooth commands to the console.

CONFIG_BT_SIGNING

This option enables data signing which is used for transferring authenticated data in an unencrypted connection.

CONFIG_BT_SMP

This option enables support for the Security Manager Protocol (SMP), making it possible to pair devices over LE.

CONFIG_BT_SMP_ALLOW_UNAUTH_OVERWRITE

This option allows all unauthenticated pairing attempts made by the peer where an unauthenticated bond already exists. This would enable cases where an attacker could copy the peer device address to connect and start an unauthenticated pairing procedure to replace the existing bond. When this option is disabled in order to create a new bond the old bond has to be explicitly deleted with bt_unpair.

CONFIG_BT_SMP_ENFORCE_MITM

With this option enabled, the Security Manager will set MITM option in the Authentication Requirements Flags whenever local IO Capabilities allow the generated key to be authenticated.

CONFIG_BT_SMP_FORCE_BREDR

This option enables SMP over BR/EDR even if controller is not supporting BR/EDR Secure Connections. This option is solely for testing and should never be enabled on production devices.

CONFIG_BT_SMP_SC_ONLY

This option enables support for Secure Connection Only Mode. In this mode device shall only use Security Mode 1 Level 4 with exception for services that only require Security Mode 1 Level 1 (no security). Security Mode 1 Level 4 stands for authenticated LE Secure Connections pairing with encryption. Enabling this option disables legacy pairing.

CONFIG_BT_SMP_SC_PAIR_ONLY

This option disables LE legacy pairing and forces LE secure connection pairing. All Security Mode 1 levels can be used with legacy pairing disabled, but pairing with devices that do not support secure connections pairing will not be supported. To force a higher security level use “Secure Connections Only Mode”

CONFIG_BT_SMP_SELFTEST

This option enables SMP self-tests executed on startup to verify security and crypto functions.

CONFIG_BT_SPI

Supports Bluetooth ICs using SPI as the communication protocol. HCI packets are sent and received as single Byte transfers, prepended after a known header. Headers may vary per device, so additional platform specific knowledge may need to be added as devices are.

CONFIG_BT_SPI_BLUENRG

Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS.

CONFIG_BT_STM32_IPM

TODO

CONFIG_BT_STORE_DEBUG_KEYS

This option enables support for storing bonds where either of devices has the Security Manager in Debug mode. This option should only be enabled for debugging and should never be used in production.

CONFIG_BT_TESTING

This option enables custom Bluetooth testing interface. Shall only be used for testing purposes.

CONFIG_BT_TICKER_COMPATIBILITY_MODE

This option enables legacy ticker scheduling which defers overlapping ticker node timeouts and thereby prevents ticker interrupts during radio RX/TX. Enabling this option disables the ticker priority- and ‘must expire’ features.

CONFIG_BT_TINYCRYPT_ECC

If this option is set TinyCrypt library is used for emulating the ECDH HCI commands and events needed by e.g. LE Secure Connections. In builds including the BLE Host, if not set the controller crypto is used for ECDH and if the controller doesn’t support the required HCI commands the LE Secure Connections support will be disabled. In builds including the HCI Raw interface and the BLE Controller, this option injects support for the 2 HCI commands required for LE Secure Connections so that Hosts can make use of those. The option defaults to enabled for a combined build with Zephyr’s own controller, since it does not have any special ECC support itself (at least not currently).

CONFIG_BT_UART

CONFIG_BT_UART_ON_DEV_NAME

This option specifies the name of UART device to be used for Bluetooth.

CONFIG_BT_USERCHAN

This driver provides access to the local Linux host’s Bluetooth adapter using a User Channel HCI socket to the Linux kernel. It is only intended to be used with the native POSIX build of Zephyr. The Bluetooth adapter must be powered off in order for Zephyr to be able to use it.

CONFIG_BT_USE_DEBUG_KEYS

This option places Security Manager in a Debug Mode. In this mode predefined Diffie-Hellman private/public key pair is used as described in Core Specification Vol. 3, Part H, 2.3.5.6.1. This option should only be enabled for debugging and should never be used in production. If this option is enabled anyone is able to decipher encrypted air traffic.

CONFIG_BT_WAIT_NOP

Emit a Command Complete event from the Controller (and wait for it from the Host) for the NOP opcode to indicate that the Controller is ready to receive commands.

CONFIG_BT_WHITELIST

This option enables the whitelist API. This takes advantage of the whitelisting feature of a BLE controller. The whitelist is a global list and the same whitelist is used by both scanner and advertiser. The whitelist cannot be modified while it is in use.

An Advertiser can whitelist which peers can connect or request scan response data. A scanner can whitelist advertiser for which it will generate advertising reports. Connections can be established automatically for whitelisted peers.

This options deprecates the bt_le_set_auto_conn API in favor of the bt_conn_create_aute_le API.

CONFIG_BUILD_NO_GAP_FILL

Don’t fill gaps in generated hex/bin/s19 files.

CONFIG_BUILD_OUTPUT_BIN

Build a binary in BIN format. This will build a zephyr.bin file need by some platforms.

CONFIG_BUILD_OUTPUT_EXE

Build a binary in ELF format that can run in the host system. This will build a zephyr.exe file.

CONFIG_BUILD_OUTPUT_HEX

Build a binary in HEX format. This will build a zephyr.hex file need by some platforms.

CONFIG_BUILD_OUTPUT_S19

Build a binary in S19 format. This will build a zephyr.s19 file need by some platforms.

CONFIG_BUILD_OUTPUT_STRIPPED

Build a stripped binary. This will build a zephyr.stripped file need by some platforms.

CONFIG_BUILTIN_STACK_GUARD

Enable Thread/Interrupt Stack Guards via built-in Stack Pointer limit checking. The functionality must be supported by HW.

CONFIG_CACHE_FLUSHING

This links in the sys_cache_flush() function, which provides a way to flush multiple lines of the d-cache. If the d-cache is present, set this to y. If the d-cache is NOT present, set this to n.

CONFIG_CACHE_LINE_SIZE

Size in bytes of a CPU d-cache line.

Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.

CONFIG_CACHE_LINE_SIZE_DETECT

This option enables querying the d-cache build register for finding the d-cache line size at the expense of taking more memory and code and a slightly increased boot time.

If the CPU’s d-cache line size is known in advance, disable this option and manually enter the value for CACHE_LINE_SIZE.

CONFIG_CAN

Enable CAN Driver Configuration

CONFIG_CAN_0

Enable CAN controller 0

CONFIG_CAN_1

Enable CAN controller 1

CONFIG_CAN_AUTO_BUS_OFF_RECOVERY

This option enables the automatic bus-off recovery according to ISO 11898-1 (recovery after 128 occurrences of 11 consecutive recessive bits). When this option is enabled, the recovery API is not available.

CONFIG_CAN_INIT_PRIORITY

CAN device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_CAN_LOG_LEVEL

CONFIG_CAN_LOG_LEVEL_DBG

Debug

CONFIG_CAN_LOG_LEVEL_ERR

Error

CONFIG_CAN_LOG_LEVEL_INF

Info

CONFIG_CAN_LOG_LEVEL_OFF

Off

CONFIG_CAN_LOG_LEVEL_WRN

Warning

CONFIG_CAN_LOOPBACK

This is a dummy driver that can only loopback messages.

CONFIG_CAN_LOOPBACK_DEV_NAME

“Device name for the loopback device”

CONFIG_CAN_MAX_FILTER

Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads.

CONFIG_CAN_MCP2515

Enable MCP2515 CAN Driver

CONFIG_CAN_MCP2515_INIT_PRIORITY

MCP2515 driver initialization priority, must be higher than SPI.

CONFIG_CAN_MCP2515_INT_THREAD_PRIO

Priority level of the internal thread which is ran for interrupt handling and incoming packets.

CONFIG_CAN_MCP2515_INT_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for interrupt handling and incoming packets.

CONFIG_CAN_MCP2515_MAX_FILTER

Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads.

CONFIG_CAN_MCUX_FLEXCAN

Enable support for mcux flexcan driver.

CONFIG_CAN_NET

Enable IPv6 Networking over can (6loCAN)

CONFIG_CAN_NET_INIT_PRIORITY

CAN NET device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_CAN_NET_LOG_LEVEL

CONFIG_CAN_NET_LOG_LEVEL_DBG

Write to log with NET_DBG or LOG_DBG in addition to previous levels.

CONFIG_CAN_NET_LOG_LEVEL_DEFAULT

Use default log level.

CONFIG_CAN_NET_LOG_LEVEL_ERR

Only write to log when NET_ERR or LOG_ERR is used.

CONFIG_CAN_NET_LOG_LEVEL_INF

Write to log with NET_INFO or LOG_INF in addition to previous levels.

CONFIG_CAN_NET_LOG_LEVEL_OFF

Do not write to log.

CONFIG_CAN_NET_LOG_LEVEL_WRN

Write to log with NET_WARN or LOG_WRN in addition to previous level.

CONFIG_CAN_NET_NAME

Name of the network device driver for IPv6 over CAN.

CONFIG_CAN_RX_TIMESTAMP

This option enables a timestamp value of the CAN free running timer. The value is incremented every bit time and starts when the controller is initialized.

CONFIG_CAN_SHELL

Enable CAN Shell for testing.

CONFIG_CAN_STM32

Enable STM32 CAN Driver. Tested on stm32F0, stm32L4 and stm32F7 series.

CONFIG_CAN_WORKQ_FRAMES_BUF_CNT

Number of frames in the buffer of a zcan_work.

CONFIG_CAVS_ICTL

These are 4 in number supporting a max of 32 interrupts each.

CONFIG_CAVS_ICTL_0_NAME

CAVS 0 Driver name

CONFIG_CAVS_ICTL_0_OFFSET

Parent interrupt number to which CAVS_0 maps

CONFIG_CAVS_ICTL_1_NAME

CAVS 1 Driver name

CONFIG_CAVS_ICTL_1_OFFSET

Parent interrupt number to which CAVS_1 maps

CONFIG_CAVS_ICTL_2_NAME

CAVS 2 Driver name

CONFIG_CAVS_ICTL_2_OFFSET

Parent interrupt number to which CAVS_2 maps

CONFIG_CAVS_ICTL_3_NAME

CAVS 3 Driver name

CONFIG_CAVS_ICTL_3_OFFSET

Parent interrupt number to which CAVS_3 maps

CONFIG_CAVS_ICTL_INIT_PRIORITY

Cavs Interrupt Logic initialization priority.

CONFIG_CAVS_ISR_TBL_OFFSET

This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned.

CONFIG_CBOR_ENCODER_NO_CHECK_USER

This option specifies whether a check user exists for a cbor encoder.

CONFIG_CBOR_FLOATING_POINT

This option enables floating point support.

CONFIG_CBOR_HALF_FLOAT_TYPE

This option enables half float type support.

CONFIG_CBOR_NO_DFLT_READER

This option specifies whether a default reader exists.

CONFIG_CBOR_NO_DFLT_WRITER

This option specifies whether a default writer exists.

CONFIG_CBOR_PARSER_MAX_RECURSIONS

This option specifies max recursions for the parser.

CONFIG_CBOR_PARSER_NO_STRICT_CHECKS

This option enables the strict parser checks.

CONFIG_CBOR_PRETTY_PRINTING

This option enables cbor_value_to_pretty_stream function.

CONFIG_CBOR_WITHOUT_OPEN_MEMSTREAM

This option enables open memstream support.

CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE

Enable the ROM bootloader backdoor which starts the bootloader if the associated pin is at the correct logic level on reset.

CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL

Set the active level of the pin selected for the bootloader backdoor.

CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN

Set the pin that is level checked if the bootloader backdoor is enabled.

CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE

Enable the serial bootloader which resides in ROM on CC13xx / CC26xx devices.

CONFIG_CC13X2_CC26X2_RTC_TIMER

This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces.

CONFIG_CC3220SF_DEBUG

Prepend debug header, disabling flash verification

CONFIG_CC3235SF_DEBUG

Prepend debug header, disabling flash verification

CONFIG_CCS811

Enable driver for CCS811 Gas sensors.

CONFIG_CDC_ACM_BULK_EP_MPS

CDC ACM class bulk endpoints size

CONFIG_CDC_ACM_IAD

IAD should not be required for non-composite CDC ACM device, but Windows 7 fails to properly enumerate without it. Enable if you want CDC ACM to work with Windows 7.

CONFIG_CDC_ACM_INTERRUPT_EP_MPS

CDC ACM class interrupt IN endpoint size

CONFIG_CDC_ECM_BULK_EP_MPS

CDC ECM class bulk endpoint size

CONFIG_CDC_ECM_INTERRUPT_EP_MPS

CDC ECM class interrupt endpoint size

CONFIG_CDC_EEM_BULK_EP_MPS

CONFIG_CFB_LOG_LEVEL

CONFIG_CFB_LOG_LEVEL_DBG

Debug

CONFIG_CFB_LOG_LEVEL_ERR

Error

CONFIG_CFB_LOG_LEVEL_INF

Info

CONFIG_CFB_LOG_LEVEL_OFF

Off

CONFIG_CFB_LOG_LEVEL_WRN

Warning

CONFIG_CHARACTER_FRAMEBUFFER

Character framebuffer for dot matrix displays.

CONFIG_CHARACTER_FRAMEBUFFER_SHELL

Activate shell module that provides Framebuffer commands to the console.

CONFIG_CHARACTER_FRAMEBUFFER_SHELL_DRIVER_NAME

Character Framebuffer Display Driver Name

CONFIG_CHARACTER_FRAMEBUFFER_USE_DEFAULT_FONTS

Use default fonts.

CONFIG_CIVETWEB

This option enables the civetweb HTTP API.

CONFIG_CLFLUSH_DETECT

This option should be enabled if it is not known in advance whether the CPU supports the CLFLUSH instruction or not.

The CPU is queried at boot time to determine which of the multiple implementations of sys_cache_flush() linked into the image is the correct one to use.

If the CPU’s support (or lack thereof) of CLFLUSH is known in advance, then disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.

CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED

An implementation of sys_cache_flush() that uses CLFLUSH is made available, instead of the one using WBINVD.

This option should only be enabled if it is known in advance that the CPU supports the CLFLUSH instruction. It disables runtime detection of CLFLUSH support thereby reducing both memory footprint and boot time.

CONFIG_CLOCK_CONTROL

Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC.

CONFIG_CLOCK_CONTROL_BEETLE

Enable driver for Reset & Clock Control subsystem found in STM32F4 family of MCUs

CONFIG_CLOCK_CONTROL_BEETLE_DEVICE_INIT_PRIORITY

This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1

CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL

Enable PLL on Beetle.

Select n if not sure.

CONFIG_CLOCK_CONTROL_LOG_LEVEL

CONFIG_CLOCK_CONTROL_LOG_LEVEL_DBG

Debug

CONFIG_CLOCK_CONTROL_LOG_LEVEL_ERR

Error

CONFIG_CLOCK_CONTROL_LOG_LEVEL_INF

Info

CONFIG_CLOCK_CONTROL_LOG_LEVEL_OFF

Off

CONFIG_CLOCK_CONTROL_LOG_LEVEL_WRN

Warning

CONFIG_CLOCK_CONTROL_MCUX_CCM

Enable support for mcux ccm driver.

CONFIG_CLOCK_CONTROL_MCUX_MCG

Enable support for mcux mcg driver.

CONFIG_CLOCK_CONTROL_MCUX_PCC

Enable support for MCUX PCC driver.

CONFIG_CLOCK_CONTROL_MCUX_SCG

Enable support for mcux scg driver.

CONFIG_CLOCK_CONTROL_MCUX_SIM

Enable support for mcux sim driver.

CONFIG_CLOCK_CONTROL_NRF

Enable support for the Nordic Semiconductor nRFxx series SoC clock driver.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_DEBUG

Enables retrieving debug information like number of performed or skipped calibrations.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP

Calibration is skipped when temperature change since last calibration was less than configured threshold. If number of consecutive skips reaches configured value then calibration is performed unconditionally. Set to 0 to perform calibration periodically regardless of temperature change.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD

Periodically, calibration action is performed. Action includes temperature measurement followed by clock calibration. Calibration may be skipped if temperature change (compared to measurement of previous calibration) did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF and number of consecutive skips did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF

Calibration is triggered if the temperature has changed by at least this amount since the last calibration.

CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the clock control driver.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_100PPM

76 ppm to 100 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM

101 ppm to 150 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM

0 ppm to 20 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM

151 ppm to 250 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_30PPM

21 ppm to 30 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM

251 ppm to 500 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_50PPM

31 ppm to 50 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_75PPM

51 ppm to 75 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING

External full swing

CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING

External low swing

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC

RC Oscillator

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION

CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH

Synthesized from HFCLK

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL

Crystal Oscillator

CONFIG_CLOCK_CONTROL_NRF_USES_TEMP_SENSOR

CONFIG_CLOCK_CONTROL_RV32M1_PCC

Enable support for RV32M1 PCC driver.

CONFIG_CLOCK_CONTROL_STM32_CUBE

Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs

CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY

This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1

CONFIG_CLOCK_STM32_AHB4_PRESCALER

HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_AHB_PRESCALER

AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_APB1_PRESCALER

APB1 Low speed clock (PCLK1) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_APB2_PRESCALER

APB2 High speed clock (PCLK2) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_CPU1_PRESCALER

CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_CPU2_PRESCALER

CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_D1CPRE

D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_D1PPRE

APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D2PPRE1

APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D2PPRE2

APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D3PPRE

APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_HPRE

hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_HSE_BYPASS

Enable this option to bypass external high-speed clock (HSE).

CONFIG_CLOCK_STM32_HSE_CLOCK

Value of external high-speed clock (HSE).

CONFIG_CLOCK_STM32_LSE

Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator.

CONFIG_CLOCK_STM32_MCO1_DIV

allowed values: 1, 2, 3, 4, 5

CONFIG_CLOCK_STM32_MCO1_SRC_HSE

Use HSE as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_HSI

Use HSI as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_LSE

Use LSE as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK

MCO1 output disabled, no clock on MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK

Use PLLCLK as source of MCO1

CONFIG_CLOCK_STM32_MCO2_DIV

allowed values: 1, 2, 3, 4, 5

CONFIG_CLOCK_STM32_MCO2_SRC_HSE

Use HSE as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK

MCO2 output disabled, no clock on MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_PLLCLK

Use PLLCLK as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_PLLI2S

Use PLLI2S as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_SYSCLK

Use SYSCLK as source of MCO2

CONFIG_CLOCK_STM32_MSI_PLL_MODE

Enable hardware auto-calibration with LSE.

CONFIG_CLOCK_STM32_MSI_RANGE

Frequency range of MSI when MSI range is provided in RCC_CR register Range 0: 100kHz Range 1: 200kHz Range 2 around 400 kHz Range 3 around 800 kHz Range 4: 1 MHz Range 5: 2 MHz Range 6: 4 MHz (reset value) Range 7: 8 MHz Range 8: 16 MHz Range 9: 24 MHz Range 10: 32 MHz Range 11: 48 MHz

CONFIG_CLOCK_STM32_PLL_DIVISOR

PLL divisor, allowed values: 2-4.

CONFIG_CLOCK_STM32_PLL_MULTIPLIER

PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz.

CONFIG_CLOCK_STM32_PLL_M_DIVISOR

PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER

PLLN multiplier factor needs to be set correctly to ensure that the VCO output frequency is between 100 and 432 MHz, except on STM32F401 where the frequency must be between 192 and 432 MHz. Allowed values: 50-432 (STM32F401: 192-432)

CONFIG_CLOCK_STM32_PLL_PREDIV

PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.

CONFIG_CLOCK_STM32_PLL_PREDIV1

PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having an HSE Oscillator available like the stm32f04xx, stm32f07xx, stm32f09xx and stm32f030xc parts. If configured on a non supported part, the HSI oscillator will be used a default PLL source and this config will be ignored. Allowed values: 1 - 16.

CONFIG_CLOCK_STM32_PLL_P_DIVISOR

PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8

CONFIG_CLOCK_STM32_PLL_Q_DIVISOR

The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15

CONFIG_CLOCK_STM32_PLL_R_DIVISOR

PLL R Output divisor, allowed values: 1-128.

CONFIG_CLOCK_STM32_PLL_SRC_HSE

Use HSE as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_HSI

Use HSI as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_MSI

Use MSI as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_PLL2

Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

CONFIG_CLOCK_STM32_PLL_XTPRE

Enable this option to enable /2 prescaler on HSE to PLL clock signal

CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE

Use HSE as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI

Use HSI as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI

Use MSI as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL

Use PLL as source of SYSCLK

CONFIG_CMSIS_MUTEX_MAX_COUNT

Mention maximum number of mutexes in CMSIS compliant application.

CONFIG_CMSIS_RTOS_V1

This enables CMSIS RTOS v1 API support. This is an OS-integration layer which allows applications using CMSIS RTOS APIs to build on Zephyr.

CONFIG_CMSIS_RTOS_V2

This enables CMSIS RTOS v2 API support. This is an OS-integration layer which allows applications using CMSIS RTOS V2 APIs to build on Zephyr.

CONFIG_CMSIS_SEMAPHORE_MAX_COUNT

Mention maximum number of semaphores in CMSIS compliant application.

CONFIG_CMSIS_THREAD_MAX_STACK_SIZE

Mention max stack size threads can be allocated in CMSIS RTOS application.

CONFIG_CMSIS_TIMER_MAX_COUNT

Mention maximum number of timers in CMSIS compliant application.

CONFIG_CMSIS_V2_EVT_FLAGS_MAX_COUNT

Mention maximum number of event flags in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_MEM_SLAB_MAX_COUNT

Mention maximum number of memory slabs in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE

Mention maximum dynamic size of memory slabs/pools in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_MSGQ_MAX_COUNT

Mention maximum number of message queues in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE

Mention maximum dynamic size of message queues in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_MUTEX_MAX_COUNT

Mention max number of mutexes in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_SEMAPHORE_MAX_COUNT

Mention max number of semaphores in CMSIS RTOS V2 compliant application.

CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT

Mention max number of dynamic threads in CMSIS RTOS V2 compliant application. There’s a limitation on the number of threads due to memory related constraints. Dynamic threads are a subset of all other CMSIS threads i.e. they also count towards that maximum too.

CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE

Mention dynamic stack size threads are allocated in CMSIS RTOS V2 application.

CONFIG_CMSIS_V2_THREAD_MAX_COUNT

Mention max number of threads in CMSIS RTOS V2 compliant application. There’s a limitation on the number of threads due to memory related constraints.

CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE

Mention max stack size threads can be allocated in CMSIS RTOS V2 application.

CONFIG_CMSIS_V2_TIMER_MAX_COUNT

Mention maximum number of timers in CMSIS RTOS V2 compliant application.

CONFIG_CMU_HFCLK_HFRCO

Set this option to use the internal high frequency RC oscillator as high frequency clock.

CONFIG_CMU_HFCLK_HFXO

Set this option to use the external high frequency crystal oscillator as high frequency clock.

CONFIG_CMU_HFCLK_LFXO

Set this option to use the external low frequency crystal oscillator as high frequency clock.

CONFIG_CMU_HFXO_FREQ

Set the external high frequency oscillator frequency in Hz. This should be set by the board’s defconfig.

CONFIG_CMU_LFXO_FREQ

Set the external low frequency oscillator frequency in Hz. This should be set by the board’s defconfig.

CONFIG_COAP

This option enables the CoAP implementation.

CONFIG_COAP_EXTENDED_OPTIONS_LEN

This option enables the parsing of extended CoAP options length. CoAP extended options length can be 2 byte value, which requires more memory. User can save memory by disabling this. That means only length of maximum 12 bytes are supported by default. Enable this if length field going to bigger that 12.

CONFIG_COAP_EXTENDED_OPTIONS_LEN_VALUE

This option specifies the maximum value of length field when COAP_EXTENDED_OPTIONS_LEN is enabled. Define the value according to user requirement.

CONFIG_COAP_INIT_ACK_TIMEOUT_MS

This value is used as a base value to retry pending CoAP packets.

CONFIG_COAP_LOG_LEVEL

CONFIG_COAP_LOG_LEVEL_DBG

Write to log with NET_DBG or LOG_DBG in addition to previous levels.

CONFIG_COAP_LOG_LEVEL_DEFAULT

Use default log level.

CONFIG_COAP_LOG_LEVEL_ERR

Only write to log when NET_ERR or LOG_ERR is used.

CONFIG_COAP_LOG_LEVEL_INF

Write to log with NET_INFO or LOG_INF in addition to previous levels.

CONFIG_COAP_LOG_LEVEL_OFF

Do not write to log.

CONFIG_COAP_LOG_LEVEL_WRN

Write to log with NET_WARN or LOG_WRN in addition to previous level.

CONFIG_COAP_TEST_API_ENABLE

Do not enable this for normal use.

CONFIG_COAP_WELL_KNOWN_BLOCK_WISE

This option enables the block wise support of CoAP response to ./well-known/core request. Without this option all resource’s information will be sent in a single IP packet (can be multiple fragments depends on MTU size). This will be useful in mesh kind of networks.

CONFIG_COAP_WELL_KNOWN_BLOCK_WISE_SIZE

Maximum size of CoAP block. Valid values are 16, 32, 64, 128, 256, 512 and 1024.

CONFIG_CODE_DATA_RELOCATION

When selected this will relocate .text, data and .bss sections from the specified files and places it in the required memory region. The files should be specified in the CMakeList.txt file with a cmake API zephyr_code_relocate().

CONFIG_CODE_DENSITY

Enable code density option to get better code density

CONFIG_CODE_FLEXSPI

Link code into external FlexSPI-controlled memory

CONFIG_CODE_FLEXSPI2

Link code into internal FlexSPI-controlled memory

CONFIG_CODE_ITCM

Link code into internal instruction tightly coupled memory (ITCM)

CONFIG_COMPAT_INCLUDES

Suppress any warnings from the pre-processor when including deprecated header files.

CONFIG_COMPILER_OPT

This option is a free-form string that is passed to the compiler when building all parts of a project (i.e. kernel). The compiler options specified by this string supplement the predefined set of compiler supplied by the build system, and can be used to change compiler optimization, warning and error messages, and so on.

CONFIG_CONSOLE

Console drivers

CONFIG_CONSOLE_GETCHAR

Character by character input and output

CONFIG_CONSOLE_GETCHAR_BUFSIZE

Buffer size for console_getchar(). The default is optimized to save RAM. You may need to increase it e.g. to support large host-side clipboard pastes. Set to 0 to disable interrupt-driven operation and use busy-polling.

CONFIG_CONSOLE_GETLINE

Line by line input

CONFIG_CONSOLE_HANDLER

This option enables console input handler allowing to write simple interaction between serial console and the OS.

CONFIG_CONSOLE_HAS_DRIVER

This is an option to be enabled by console drivers to signal that some kind of console exists.

CONFIG_CONSOLE_INPUT_MAX_LINE_LEN

This option can be used to modify the maximum length a console input can be.

CONFIG_CONSOLE_PUTCHAR_BUFSIZE

Buffer size for console_putchar(). The default is optimized to save RAM. You may need to increase it e.g. to support large host-side clipboard pastes. Set to 0 to disable interrupt-driven operation and use busy-polling.

CONFIG_CONSOLE_SUBSYS

Console subsystem and helper functions

CONFIG_COOP_ENABLED

CONFIG_CORTEX_M_SYSTICK

This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces.

CONFIG_COUNTER

Enable support for counter and timer.

CONFIG_COUNTER_CMOS

Counter driver for x86 CMOS/RTC clock

CONFIG_COUNTER_GECKO_RTCC

Enable counter driver based on RTCC module for Silicon Labs Gecko chips.

CONFIG_COUNTER_IMX_EPIT

Enable the IMX EPIT driver.

CONFIG_COUNTER_IMX_EPIT_1

Enable Counter 1.

CONFIG_COUNTER_IMX_EPIT_2

Enable Counter 2.

CONFIG_COUNTER_LOG_LEVEL

CONFIG_COUNTER_LOG_LEVEL_DBG

Debug

CONFIG_COUNTER_LOG_LEVEL_ERR

Error

CONFIG_COUNTER_LOG_LEVEL_INF

Info

CONFIG_COUNTER_LOG_LEVEL_OFF

Off

CONFIG_COUNTER_LOG_LEVEL_WRN

Warning

CONFIG_COUNTER_MCUX_GPT

Enable support for mcux General Purpose Timer (GPT) driver.

CONFIG_COUNTER_MCUX_GPT1

Enable Counter on GPT1

CONFIG_COUNTER_MCUX_GPT2

Enable Counter on GPT2

CONFIG_COUNTER_MCUX_RTC

Enable support for mcux rtc driver.

CONFIG_COUNTER_NRF_RTC

CONFIG_COUNTER_NRF_TIMER

CONFIG_COUNTER_RTC0

Enable Counter on RTC0

CONFIG_COUNTER_RTC1

Enable Counter on RTC1

CONFIG_COUNTER_RTC2

Enable Counter on RTC2

CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT

CONFIG_COUNTER_RTC_STM32

Build RTC driver for STM32 SoCs. Tested on STM32 F3, F4, L4, F7, G4 series

CONFIG_COUNTER_RTC_STM32_CLOCK_LSE

Use LSE as RTC clock

CONFIG_COUNTER_RTC_STM32_CLOCK_LSI

Use LSI as RTC clock

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_HIGH

Xtal mode higher driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_LOW

Xtal mode lower driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMHIGH

Xtal mode medium high driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMLOW

Xtal mode medium low driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_STRENGTH

CONFIG_COUNTER_RTC_WITH_PPI_WRAP

CONFIG_COUNTER_SAM0_TC32

Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode.

CONFIG_COUNTER_SAM0_TC32_0_DIVISOR

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_2_DIVISOR

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_4_DIVISOR

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_6_DIVISOR

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_8

clock / 8

CONFIG_COUNTER_TIMER0

Enable Counter on TIMER0

CONFIG_COUNTER_TIMER1

Enable Counter on TIMER1

CONFIG_COUNTER_TIMER2

Enable Counter on TIMER2

CONFIG_COUNTER_TIMER3

Enable Counter on TIMER3

CONFIG_COUNTER_TIMER4

Enable Counter on TIMER4

CONFIG_COUNTER_XEC

Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU.

CONFIG_COVERAGE

This option will build your application with the -coverage option which will generate data that can be used to create coverage reports. For more information see https://docs.zephyrproject.org/latest/guides/coverage.html

CONFIG_COVERAGE_GCOV

This option will select the custom gcov library. The reports will be available over serial. This serial dump can be passed to gen_gcov_files.py which creates the required .gcda files. These can be read by gcov utility. For more details see gcovr.com .

CONFIG_CPLUSPLUS

This option enables the use of applications built with C++.

CONFIG_CPU_APOLLO_LAKE

This option signifies the use of a CPU from the Apollo Lake family.

CONFIG_CPU_ARCEM

This option signifies the use of an ARC EM CPU

CONFIG_CPU_ARCHS

This option signifies the use of an ARC HS CPU

CONFIG_CPU_ARCV2

This option signifies the use of a CPU of the ARCv2 family.

CONFIG_CPU_ATOM

This option signifies the use of a CPU from the Atom family.

CONFIG_CPU_CORTEX

This option signifies the use of a CPU of the Cortex family.

CONFIG_CPU_CORTEX_M

This option signifies the use of a CPU of the Cortex-M family.

CONFIG_CPU_CORTEX_M0

This option signifies the use of a Cortex-M0 CPU

CONFIG_CPU_CORTEX_M0PLUS

This option signifies the use of a Cortex-M0+ CPU

CONFIG_CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP

This option signifies the Cortex-M0 has some mechanisms that can map the vector table to SRAM

CONFIG_CPU_CORTEX_M23

This option signifies the use of a Cortex-M23 CPU

CONFIG_CPU_CORTEX_M3

This option signifies the use of a Cortex-M3 CPU

CONFIG_CPU_CORTEX_M33

This option signifies the use of a Cortex-M33 CPU

CONFIG_CPU_CORTEX_M4

This option signifies the use of a Cortex-M4 CPU

CONFIG_CPU_CORTEX_M7

This option signifies the use of a Cortex-M7 CPU

CONFIG_CPU_CORTEX_M_HAS_BASEPRI

This option signifies the CPU has the BASEPRI register.

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Always present in CPUs that implement the ARMv7-M or ARM8-M Mainline architectures.

CONFIG_CPU_CORTEX_M_HAS_CMSE

This option signifies the Cortex-M CPU has the CMSE intrinsics.

CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS

This option signifies the CPU may trigger system faults (other than HardFault) with configurable priority, and, therefore, it needs to reserve a priority level for them.

CONFIG_CPU_CORTEX_M_HAS_SPLIM

This option signifies the CPU has the MSPLIM, PSPLIM registers.

The stack pointer limit registers, MSPLIM, PSPLIM, limit the extend to which the Main and Process Stack Pointers, respectively, can descend. MSPLIM, PSPLIM are always present in ARMv8-M MCUs that implement the ARMv8-M Main Extension (Mainline).

In an ARMv8-M Mainline implementation with the Security Extension the MSPLIM, PSPLIM registers have additional Secure instances. In an ARMv8-M Baseline implementation with the Security Extension the MSPLIM, PSPLIM registers have only Secure instances.

CONFIG_CPU_CORTEX_M_HAS_SYSTICK

This option is enabled when the CPU implements the SysTick timer.

CONFIG_CPU_CORTEX_M_HAS_VTOR

This option signifies the CPU has the VTOR register. The VTOR indicates the offset of the vector table base address from memory address 0x00000000. Always present in CPUs implementing the ARMv7-M or ARMv8-M architectures. Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline architectures (except for Cortex-M0, where it is never implemented).

CONFIG_CPU_CORTEX_R

This option signifies the use of a CPU of the Cortex-R family.

CONFIG_CPU_CORTEX_R4

This option signifies the use of a Cortex-R4 CPU

CONFIG_CPU_CORTEX_R5

This option signifies the use of a Cortex-R5 CPU

CONFIG_CPU_EM4

If y, the SoC uses an ARC EM4 CPU

CONFIG_CPU_EM4_DMIPS

If y, the SoC uses an ARC EM4 DMIPS CPU

CONFIG_CPU_EM4_FPUDA

If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions

CONFIG_CPU_EM4_FPUS

If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision floating-point extension

CONFIG_CPU_EM6

If y, the SoC uses an ARC EM6 CPU

CONFIG_CPU_HAS_ARM_MPU

This option is enabled when the CPU has a Memory Protection Unit (MPU) in ARM flavor.

CONFIG_CPU_HAS_ARM_SAU

MCU implements the ARM Security Attribution Unit (SAU).

CONFIG_CPU_HAS_FPU

This option is enabled when the CPU has hardware floating point unit.

CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION

When enabled, indicates that the SoC has a double floating point precision unit.

CONFIG_CPU_HAS_MPU

This option is enabled when the CPU has a Memory Protection Unit (MPU).

CONFIG_CPU_HAS_NRF_IDAU

MCU implements the nRF (vendor-specific) Security Attribution Unit. (IDAU: “Implementation-Defined Attribution Unit”, in accordance with ARM terminology).

CONFIG_CPU_HAS_NXP_MPU

This option is enabled when the CPU has a Memory Protection Unit (MPU) in NXP flavor.

CONFIG_CPU_HAS_TEE

This option is enabled when the CPU has support for Trusted Execution Environment (e.g. when it has a security attribution unit).

CONFIG_CPU_MINUTEIA

This option signifies the use of a CPU from the Minute IA family.

CONFIG_CPU_NIOS2_GEN2

This option signifies the use of a Nios II Gen 2 CPU

CONFIG_CRYPTO

Crypto Drivers [EXPERIMENTAL]

CONFIG_CRYPTO_ATAES132A

Enable Atmel ATAES132A 32k AES Serial EEPROM support.

CONFIG_CRYPTO_ATAES132A_DRV_NAME

Name for the ATAES132A driver which will be used for binding.

CONFIG_CRYPTO_ATAES132A_I2C_ADDR

ATAES132A chip’s I2C address.

CONFIG_CRYPTO_ATAES132A_I2C_PORT_NAME

Master I2C port name through which ATAES132A chip is accessed.

CONFIG_CRYPTO_ATAES132A_I2C_SPEED_FAST

Fast bus speed of up to 400KHz.

CONFIG_CRYPTO_ATAES132A_I2C_SPEED_STANDARD

Standard bis speed of up to 100KHz.

CONFIG_CRYPTO_INIT_PRIORITY

Crypto devices initialization priority.

CONFIG_CRYPTO_LOG_LEVEL

CONFIG_CRYPTO_LOG_LEVEL_DBG

Debug

CONFIG_CRYPTO_LOG_LEVEL_ERR

Error

CONFIG_CRYPTO_LOG_LEVEL_INF

Info

CONFIG_CRYPTO_LOG_LEVEL_OFF

Off

CONFIG_CRYPTO_LOG_LEVEL_WRN

Warning

CONFIG_CRYPTO_MBEDTLS_SHIM

Enable mbedTLS shim layer compliant with crypto APIs. You will need to fill in a relevant value to CONFIG_MBEDTLS_HEAP_SIZE.

CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME

Device name for mbedTLS Pseudo device.

CONFIG_CRYPTO_MBEDTLS_SHIM_MAX_SESSION

This can be used to tweak the amount of sessions the driver can handle in parallel.

CONFIG_CRYPTO_TINYCRYPT_SHIM

Enable TinyCrypt shim layer compliant with crypto APIs.

CONFIG_CRYPTO_TINYCRYPT_SHIM_DRV_NAME

Device name for TinyCrypt Pseudo device.

CONFIG_CRYPTO_TINYCRYPT_SHIM_MAX_SESSION

This can be used to tweak the amount of sessions the driver can handle in parallel.

CONFIG_CSPRING_ENABLED

CONFIG_CS_CTR_DRBG_PERSONALIZATION

Personalization data can be provided in addition to the entropy source to make the initialization of the CTR-DRBG as unique as possible.

CONFIG_CTR_DRBG_CSPRNG_GENERATOR

Enables the CTR-DRBG pseudo-random number generator. This CSPRNG shall use the entropy API for an initialization seed. The CTR-DRBG is a a FIPS140-2 recommended cryptographically secure random number generator.

CONFIG_CUSTOM_LINKER_SCRIPT

Path to the linker script to be used instead of the one define by the board.

The linker script must be based on a version provided by Zephyr since the kernel can expect a certain layout/certain regions.

This is useful when an application needs to add sections into the linker script and avoid having to change the script provided by Zephyr.

CONFIG_CUSTOM_RODATA_LD

Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional data and linker directives into the rodata section.

CONFIG_CUSTOM_RWDATA_LD

Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional data and linker directives into the data section.

CONFIG_CUSTOM_SECTIONS_LD

Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional arbitrary sections.

CONFIG_CUSTOM_SECTION_ALIGN

MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory wasting in linker scripts defined memory sections. Use this symbol to guarantee user custom section align size to avoid more memory used for respect alignment. But that needs carefully configure MPU region and sub-regions(ARMv7-M) to cover this feature.

CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE

Custom align size of memory section in linker scripts. Usually it should consume less alignment memory. Although this alignment size is configured by users, it must also respect the power of two regulation if hardware requires.

CONFIG_DATA_DTCM

Link data into internal data tightly coupled memory (DTCM)

CONFIG_DATA_OCRAM

Link data into On-Chip RAM memory

CONFIG_DATA_SEMC

Link data into external SEMC-controlled memory

CONFIG_DEBUG

Build a kernel suitable for debugging. Right now, this option only disables optimization, more debugging variants can be selected from here to allow more debugging.

CONFIG_DEBUG_INFO

This option enables the addition of various information that can be used by debuggers in debugging the system, or enable additional debugging information to be reported at runtime.

CONFIG_DEBUG_OPTIMIZATIONS

Compiler optimizations will be set to -Og independently of other options.

CONFIG_DEVICE_CONFIGURATION_DATA

Device configuration data (DCD) provides a sequence of commands to the boot ROM to initialize components such as an SDRAM.

CONFIG_DEVICE_IDLE_PM

Enable device Idle Power Management to save power. With device Idle PM enabled, devices can be suspended or resumed based on the device usage even while the CPU or system is running.

CONFIG_DEVICE_POWER_MANAGEMENT

This option enables the device power management interface. The interface consists of hook functions implemented by device drivers that get called by the power manager application when the system is going to suspend state or resuming from suspend state. This allows device drivers to do any necessary power management operations like turning off device clocks and peripherals. The device drivers may also save and restore states in these hook functions.

CONFIG_DEVICE_SHELL

This shell provides access to basic device data.

CONFIG_DHT

Enable driver for the DHT temperature and humidity sensor family.

CONFIG_DHT_CHIP_DHT11

Choose this option to enable the DHT11 chip.

CONFIG_DHT_CHIP_DHT22

Choose this option to enable the DHT22 chip.

CONFIG_DHT_GPIO_DEV_NAME

The device name of the GPIO device to which the chip’s data pin is connected.

CONFIG_DHT_GPIO_PIN_NUM

The number of the GPIO on which the chip’s data pin is connected.

CONFIG_DHT_NAME

Device name with which the sensor is identified.

CONFIG_DISABLE_SSBD

This option will disable Speculative Store Bypass in order to mitigate against certain kinds of side channel attacks. Quoting the “Speculative Execution Side Channels” document, version 2.0:

When SSBD is set, loads will not execute speculatively until the addresses of all older stores are known. This ensure s that a load does not speculatively consume stale data values due to bypassing an older store on the same logical processor.

If enabled, this applies to all threads in the system.

Even if enabled, will have no effect on CPUs that do not require this feature.

CONFIG_DISK_ACCESS

Enable disk access over a supported media backend like FLASH or RAM

CONFIG_DISK_ACCESS_FLASH

Flash device is used for the file system.

CONFIG_DISK_ACCESS_RAM

RAM buffer used to emulate storage disk. This option can be used to test the file system.

CONFIG_DISK_ACCESS_SDHC

File system on a SDHC card.

CONFIG_DISK_ACCESS_SPI_SDHC

File system on a SDHC card accessed over SPI.

CONFIG_DISK_ACCESS_USDHC

File system on a SDHC card accessed over NXP USDHC.

CONFIG_DISK_ACCESS_USDHC1

File system on a SDHC card accessed over USDHC instance 1.

CONFIG_DISK_ACCESS_USDHC2

File system on a SDHC card accessed over USDHC instance 2.

CONFIG_DISK_ERASE_BLOCK_SIZE

This is typically the minimum block size that is erased at one time in flash storage. Typically it is equal to the flash memory page size.

CONFIG_DISK_FLASH_DEV_NAME

Flash device name to be used as storage backend

CONFIG_DISK_FLASH_ERASE_ALIGNMENT

This is the start address alignment required by the flash component.

CONFIG_DISK_FLASH_MAX_RW_SIZE

This is the maximum number of bytes that the flash_write API can accept per invocation. API.

CONFIG_DISK_FLASH_START

This is start address of the flash to be used as storage backend.

CONFIG_DISK_FLASH_VOLUME_NAME

Disk name as per file system naming guidelines.

CONFIG_DISK_LOG_LEVEL

CONFIG_DISK_LOG_LEVEL_DBG

Debug

CONFIG_DISK_LOG_LEVEL_ERR

Error

CONFIG_DISK_LOG_LEVEL_INF

Info

CONFIG_DISK_LOG_LEVEL_OFF

Off

CONFIG_DISK_LOG_LEVEL_WRN

Warning

CONFIG_DISK_RAM_VOLUME_NAME

Disk name as per file system naming guidelines.

CONFIG_DISK_RAM_VOLUME_SIZE

Size of the RAM Disk.

CONFIG_DISK_SDHC_VOLUME_NAME

Disk name as per file system naming guidelines.

CONFIG_DISK_VOLUME_SIZE

This is the file system volume size in bytes.

CONFIG_DISPLAY

Enable display drivers

CONFIG_DISPLAY_LOG_LEVEL

CONFIG_DISPLAY_LOG_LEVEL_DBG

Debug

CONFIG_DISPLAY_LOG_LEVEL_ERR

Error

CONFIG_DISPLAY_LOG_LEVEL_INF

Info

CONFIG_DISPLAY_LOG_LEVEL_OFF

Off

CONFIG_DISPLAY_LOG_LEVEL_WRN

Warning

CONFIG_DISPLAY_MCUX_ELCDIF

Enable support for mcux eLCDIF driver.

CONFIG_DMA

DMA driver Configuration

CONFIG_DMA_0_IRQ_PRI

IRQ Priority for the DMA Controller.

CONFIG_DMA_0_NAME

Device name for DMA Controller 0.

CONFIG_DMA_1_NAME

Device name for DMA Controller 1.

CONFIG_DMA_2_NAME

Device name for DMA Controller 2.

CONFIG_DMA_CAVS

CAVS DMA driver.

CONFIG_DMA_LOG_LEVEL

CONFIG_DMA_LOG_LEVEL_DBG

Debug

CONFIG_DMA_LOG_LEVEL_ERR

Error

CONFIG_DMA_LOG_LEVEL_INF

Info

CONFIG_DMA_LOG_LEVEL_OFF

Off

CONFIG_DMA_LOG_LEVEL_WRN

Warning

CONFIG_DMA_NIOS2_MSGDMA

Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver.

CONFIG_DMA_SAM0

DMA driver for Atmel SAM0 series MCUs.

CONFIG_DMA_SAM_XDMAC

Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver.

CONFIG_DMA_STM32

DMA driver for STM32 series SoCs.

CONFIG_DMA_STM32_V1

Enable DMA support on F2/F4/F7 series SoCs.

CONFIG_DMA_STM32_V2

Enable DMA support on F0/F1/F3/L0/L4 series SoCs.

CONFIG_DNS_NUM_CONCUR_QUERIES

This defines how many concurrent DNS queries can be generated using same DNS context. Normally 1 is a good default value.

CONFIG_DNS_RESOLVER

This option enables the DNS client side support for Zephyr

CONFIG_DNS_RESOLVER_ADDITIONAL_BUF_CTR

Number of additional buffers available for the DNS resolver. The DNS resolver requires at least one buffer. This option enables additional buffers required for multiple concurrent DNS connections.

CONFIG_DNS_RESOLVER_ADDITIONAL_QUERIES

Number of additional DNS queries that the DNS resolver may generate when the RR ANSWER only contains CNAME(s). The maximum value of this variable is constrained to avoid ‘alias loops’.

CONFIG_DNS_RESOLVER_LOG_LEVEL

CONFIG_DNS_RESOLVER_LOG_LEVEL_DBG

Write to log with NET_DBG or LOG_DBG in addition to previous levels.

CONFIG_DNS_RESOLVER_LOG_LEVEL_DEFAULT

Use default log level.

CONFIG_DNS_RESOLVER_LOG_LEVEL_ERR

Only write to log when NET_ERR or LOG_ERR is used.

CONFIG_DNS_RESOLVER_LOG_LEVEL_INF

Write to log with NET_INFO or LOG_INF in addition to previous levels.

CONFIG_DNS_RESOLVER_LOG_LEVEL_OFF

Do not write to log.

CONFIG_DNS_RESOLVER_LOG_LEVEL_WRN

Write to log with NET_WARN or LOG_WRN in addition to previous level.

CONFIG_DNS_RESOLVER_MAX_SERVERS

Max number of DNS servers that we can connect to. Normally one DNS server is enough. Each connection to DNS server will use one network context.

CONFIG_DNS_SERVER1

DNS server IP address 1. The address can be either IPv4 or IPv6 address. An optional port number can be given. Following syntax is supported: 192.0.2.1 192.0.2.1:5353 2001:db8::1 [2001:db8::1]:5353 It is not mandatory to use this Kconfig option at all. The one calling dns_resolve_init() can use this option or not to populate the server list. If the DNS server addresses are set here, then we automatically create default DNS context for the user.

CONFIG_DNS_SERVER2

See help in “DNS server 1” option.

CONFIG_DNS_SERVER3

See help in “DNS server 1” option.

CONFIG_DNS_SERVER4

See help in “DNS server 1” option.

CONFIG_DNS_SERVER5

See help in “DNS server 1” option.

CONFIG_DNS_SERVER_IP_ADDRESSES

Allow DNS IP addresses to be set in config file for networking applications.

CONFIG_DUMMY_DISPLAY

Enable dummy display driver compliant with display driver API.

CONFIG_DUMMY_DISPLAY_DEV_NAME

Dummy display device name

CONFIG_DUMMY_DISPLAY_X_RES

X resolution for dummy display

CONFIG_DUMMY_DISPLAY_Y_RES

Y resolution for dummy display

CONFIG_DW_ICTL

Designware Interrupt Controller can be used as a 2nd level interrupt controller which combines several sources of interrupt into one line that is then routed to the 1st level interrupt controller.

CONFIG_DW_ICTL_INIT_PRIORITY

DesignWare Interrupt Controller initialization priority.

CONFIG_DW_ICTL_NAME

Give a name for the instance of Designware Interrupt Controller

CONFIG_DW_ICTL_OFFSET

Parent interrupt number to which DW_ICTL maps

CONFIG_DW_ISR_TBL_OFFSET

This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned.

CONFIG_DYNAMIC_INTERRUPTS

Enable installation of interrupts at runtime, which will move some interrupt-related data structures to RAM instead of ROM, and on some architectures increase code size.

CONFIG_DYNAMIC_OBJECTS

Enabling this option allows for kernel objects to be requested from the calling thread’s resource pool, at a slight cost in performance due to the supplemental run-time tables required to validate such objects.

Objects allocated in this way can be freed with a supervisor-only API call, or when the number of references to that object drops to zero.

CONFIG_EAGER_FP_SHARING

This hidden option unconditionally saves/restores the FPU/SIMD register state on every context switch.

Mitigates CVE-2018-3665, but incurs a performance hit.

For vulnerable systems that process sensitive information in the FPU register set, should be used any time CONFIG_FLOAT is enabled, regardless if the FPU is used by one thread or multiple.

CONFIG_EARLY_CONSOLE

This option will enable stdout as early as possible, for debugging purpose. For instance, in case of STDOUT_CONSOLE being set it will initialize its driver earlier than normal, in order to get the stdout sent through the console at the earliest stage possible.

CONFIG_EEPROM

Enable support for EEPROM hardware.

CONFIG_EEPROM_AT24

Enable support for Atmel AT24 (and compatible) I2C EEPROMs.

CONFIG_EEPROM_AT25

Enable support for Atmel AT25 (and compatible) SPI EEPROMs.

CONFIG_EEPROM_AT2X

Enable support for Atmel AT2x (and compatible) I2C/SPI EEPROMs.

CONFIG_EEPROM_LOG_LEVEL

CONFIG_EEPROM_LOG_LEVEL_DBG

Debug

CONFIG_EEPROM_LOG_LEVEL_ERR

Error

CONFIG_EEPROM_LOG_LEVEL_INF

Info

CONFIG_EEPROM_LOG_LEVEL_OFF

Off

CONFIG_EEPROM_LOG_LEVEL_WRN

Warning

CONFIG_EEPROM_NATIVE_POSIX

Enable Native POSIX EEPROM driver.

CONFIG_EEPROM_SHELL

Enable the EEPROM shell with EEPROM related commands.

CONFIG_EEPROM_SHELL_BUFFER_SIZE

Size of the buffer used for EEPROM read/write commands in the EEPROM shell.

CONFIG_ENABLE_EXTENDED_IBRS

This option will enable the Extended Indirect Branch Restricted Speculation ‘always on’ feature. This mitigates Indirect Branch Control vulnerabilities (aka Spectre V2).

CONFIG_ENABLE_HID_INT_OUT_EP

Enable USB HID Device Interrupt OUT Endpoint.

CONFIG_ENS210

Enable driver for ENS210 Digital Temperature and Humidity sensor.

CONFIG_ENS210_CRC_CHECK

Check the crc value after data reading.

CONFIG_ENS210_MAX_READ_RETRIES

Number of retries when value reading failed, value not valid or crc not ok.

CONFIG_ENS210_MAX_STAT_RETRIES

Number of retries when status reading failed or device not ready.

CONFIG_ENTROPY_CC13XX_CC26XX_ALARM_THRESHOLD

The number of samples detected with repeating patterns before an alarm event is triggered. The associated FRO is automatically shut down.

CONFIG_ENTROPY_CC13XX_CC26XX_POOL_SIZE

The size in bytes of the buffer used to store entropy generated by the hardware. Should be a power of two for high performance.

CONFIG_ENTROPY_CC13XX_CC26XX_RNG

This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs.

CONFIG_ENTROPY_CC13XX_CC26XX_SAMPLES_PER_CYCLE

The number of samples used to generate entropy. The time required to generate 64 bits of entropy is determined by the number of FROs enabled, the sampling (system) clock frequency, and this value.

CONFIG_ENTROPY_CC13XX_CC26XX_SHUTDOWN_THRESHOLD

The number of FROs allowed to be shutdown before the driver attempts to take corrective action.

CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR

Enables a random number generator that uses the enabled hardware entropy gathering driver to generate random numbers. Should only be selected if hardware entropy driver is designed to be a random number generator source.

CONFIG_ENTROPY_ESP32_RNG

This option enables the entropy number generator for ESP32 SoCs.

With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator.

CONFIG_ENTROPY_GENERATOR

Include entropy drivers in system config.

CONFIG_ENTROPY_HAS_DRIVER

This is an option to be enabled by individual entropy driver to signal that there is a true entropy driver.

CONFIG_ENTROPY_MCUX_RNGA

This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver.

CONFIG_ENTROPY_MCUX_TRNG

This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver.

CONFIG_ENTROPY_NAME

Specify the device name to be used for the ENTROPY driver.

CONFIG_ENTROPY_NRF5_BIAS_CORRECTION

This option enables the RNG bias correction, which guarantees a uniform distribution of 0 and 1. When this option is enabled, the time to generate a byte cannot be guaranteed.

CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE

Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2.

CONFIG_ENTROPY_NRF5_ISR_THRESHOLD

Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started.

CONFIG_ENTROPY_NRF5_PRI

nRF5X RNG IRQ priority.

CONFIG_ENTROPY_NRF5_RNG

This option enables the RNG peripheral, which is a random number generator, based on internal thermal noise, that provides a random 8-bit value to the host when read.

CONFIG_ENTROPY_NRF5_THR_POOL_SIZE

Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2.

CONFIG_ENTROPY_NRF5_THR_THRESHOLD

Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started.

CONFIG_ENTROPY_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the entropy driver.

CONFIG_ENTROPY_RV32M1_TRNG

This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver.

CONFIG_ENTROPY_SAM_RNG

Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs.

CONFIG_ENTROPY_STM32_RNG

This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7 and G4 series.

CONFIG_ERRNO

Enable per-thread errno in the kernel. Application and library code must include errno.h provided by the C library (libc) to use the errno symbol. The C library must access the per-thread errno via the _get_errno() symbol.

CONFIG_ESPI

Enable ESPI Driver.

CONFIG_ESPI_FLASH_CHANNEL

eSPI Controller supports flash channel.

CONFIG_ESPI_INIT_PRIORITY

IRQ Priority for ESPI Controller.

CONFIG_ESPI_LOG_LEVEL

CONFIG_ESPI_LOG_LEVEL_DBG

Debug

CONFIG_ESPI_LOG_LEVEL_ERR

Error

CONFIG_ESPI_LOG_LEVEL_INF

Info

CONFIG_ESPI_LOG_LEVEL_OFF

Off

CONFIG_ESPI_LOG_LEVEL_WRN

Warning

CONFIG_ESPI_OOB_CHANNEL

eSPI Controller supports OOB channel.

CONFIG_ESPI_PERIPHERAL_8042_KBC

Enables 8042 keyboard controller over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_CHANNEL

eSPI Controller supports peripheral channel.

CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80

Enables debug Port 80 over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_HOST_IO

Enables ACPI Host I/O over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_PORT_92

Enables legacy Port 92 over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_UART

Enables UART over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING

This tells the driver to which SoC UART to direct the UART traffic send over eSPI from host.

CONFIG_ESPI_SLAVE

Enables eSPI driver in slave mode.

CONFIG_ESPI_VWIRE_CHANNEL

eSPI Controller supports virtual wires channel.

CONFIG_ESPI_XEC

Enable the Microchip XEC ESPI driver.

CONFIG_ETHERNET_LOG_LEVEL

CONFIG_ETHERNET_LOG_LEVEL_DBG

Write to log with NET_DBG or LOG_DBG in addition to previous levels.

CONFIG_ETHERNET_LOG_LEVEL_DEFAULT

Use default log level.

CONFIG_ETHERNET_LOG_LEVEL_ERR

Only write to log when NET_ERR or LOG_ERR is used.

CONFIG_ETHERNET_LOG_LEVEL_INF

Write to log with NET_INFO or LOG_INF in addition to previous levels.

CONFIG_ETHERNET_LOG_LEVEL_OFF

Do not write to log.

CONFIG_ETHERNET_LOG_LEVEL_WRN

Write to log with NET_WARN or LOG_WRN in addition to previous level.

CONFIG_ETH_E1000

Enable Intel(R) PRO/1000 Gigabit Ethernet driver.

CONFIG_ETH_ENC28J60

ENC28J60C Stand-Alone Ethernet Controller with SPI Interface

CONFIG_ETH_ENC28J60_0

Include port 0 driver

CONFIG_ETH_ENC28J60_0_FULL_DUPLEX

Enable Full Duplex. Device is configured half duplex when disabled.

CONFIG_ETH_ENC28J60_0_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_ETH_ENC28J60_RX_THREAD_PRIO

Priority level for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC28J60_RX_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC28J60_TIMEOUT

Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped.

CONFIG_ETH_ENC424J600

ENC424J600C Stand-Alone Ethernet Controller with SPI Interface

CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_ETH_ENC424J600_RX_THREAD_PRIO

Priority level for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC424J600_RX_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC424J600_TIMEOUT

Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped.

CONFIG_ETH_INIT_PRIORITY

Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_ETH_LITEETH

LiteEth Ethernet core driver

CONFIG_ETH_LITEETH_0

LiteEth Ethernet port 0

CONFIG_ETH_LITEETH_0_IRQ_PRI

IRQ priority

CONFIG_ETH_LITEETH_0_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_MCUX

Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change.

CONFIG_ETH_MCUX_0

Include port 0 driver

CONFIG_ETH_MCUX_0_MANUAL_MAC

Manual MAC address

CONFIG_ETH_MCUX_0_RANDOM_MAC

Generate a random MAC address dynamically on each reboot. Note that using this choice and rebooting a board may leave stale MAC address in peers’ ARP caches and lead to issues and delays in communication. (Use “ip neigh flush all” on Linux peers to clear ARP cache.)

CONFIG_ETH_MCUX_0_UNIQUE_MAC

Generate MAC address from MCU’s unique identification register.

CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG

Enable additional PHY related debug information related to PHY status polling.

CONFIG_ETH_MCUX_PHY_TICK_MS

Set the PHY status polling period.

CONFIG_ETH_MCUX_PROMISCUOUS_MODE

Place the Ethernet receiver in promiscuous mode. This may be useful for debugging and not needed for normal work.

CONFIG_ETH_MCUX_PTP_CLOCK_SRC_HZ

Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate.

CONFIG_ETH_MCUX_PTP_RX_BUFFERS

Set the number of RX buffers provided to the MCUX driver to store timestamps.

CONFIG_ETH_MCUX_PTP_TX_BUFFERS

Set the number of TX buffers provided to the MCUX driver to store timestamps.

CONFIG_ETH_MCUX_RX_BUFFERS

Set the number of RX buffers provided to the MCUX driver.

CONFIG_ETH_MCUX_TX_BUFFERS

Set the number of TX buffers provided to the MCUX driver.

CONFIG_ETH_NATIVE_POSIX

Enable native posix ethernet driver. Note, this driver is run inside a process in your host system.

CONFIG_ETH_NATIVE_POSIX_DEV_NAME

This option sets the TUN/TAP device name in your host system.

CONFIG_ETH_NATIVE_POSIX_DRV_NAME

This option sets the driver name and name of the network interface in your host system.

CONFIG_ETH_NATIVE_POSIX_MAC_ADDR

Specify a MAC address for the ethernet interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random.

CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK

Enable PTP clock support.

CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_NATIVE_POSIX_SETUP_SCRIPT

This option sets the name of the script that is run when the host TAP network interface is created. The script should setup IP addresses etc. for the host TAP network interface. The default script accepts following options: -i|–interface <network interface name>, default is zeth -f|–file <config file name>, default is net_setup_host.conf If needed, you can add these options to this script name option. Note that the driver will add -i option with the value of CONFIG_ETH_NATIVE_POSIX_DRV_NAME option to the end of the options list when calling the host setup script.

CONFIG_ETH_NATIVE_POSIX_STARTUP_AUTOMATIC

If set, the native_posix ethernet driver will set up the network interface, requiring zephyr.exe to be run with root privileges (needed to create and configure the TAP device). If not set (the default and recommended way), the network interface must be set up manually using net-setup.sh (from the net-tools project repo). The zephyr.exe program can then be run as a non-root user.

CONFIG_ETH_NATIVE_POSIX_STARTUP_SCRIPT

This option sets the name of the script that is run when the host TAP network interface is created and setup script has been run. The startup script could launch e.g., wireshark to capture the network traffic for the freshly started network interface. Note that the network interface name CONFIG_ETH_NATIVE_POSIX_DRV_NAME is appended at the end of this startup script name. Example script for starting wireshark is provided in ${ZEPHYR_BASE}/samples/net/eth_native_posix/net_start_wireshark.sh file.

CONFIG_ETH_NATIVE_POSIX_STARTUP_SCRIPT_USER

By default the startup script is run as a root user. Set here the username to run the script if running it as a root user is not desired. Note that this setting is only for startup script and not for the setup script. The setup script needs to be run always as a root user.

CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP

Native posix ethernet driver will strip of VLAN tag from Rx Ethernet frames and sets tag information in net packet metadata.

CONFIG_ETH_NIC_MODEL

Tells what Qemu network model to use. This value is given as a parameter to -nic qemu command line option.

CONFIG_ETH_SAM_GMAC

Enable Atmel SAM MCU Family Ethernet driver.

CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT

Number of network buffers that will be permanently allocated by the Ethernet driver. These buffers are used in receive path. They are preallocated by the driver and made available to the GMAC module to be filled in with incoming data. Their number has to be large enough to fit at least one complete Ethernet frame. SAM ETH driver will always allocate that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT which is a total amount of RX data buffers used by the whole networking stack. One has to ensure that NET_PKT_RX_COUNT is large enough to fit at least two Ethernet frames: one being received by the GMAC module and the other being processed by the higher layer networking stack.

CONFIG_ETH_SAM_GMAC_FORCED_QUEUE

Which queue to force the routing to. This affects both the TX and RX queues setup.

CONFIG_ETH_SAM_GMAC_FORCE_QUEUE

This option is meant to be used only for debugging. Use it to force all traffic to be routed through a specific hardware queue. With this enabled it is easier to verify whether the chosen hardware queue actually works. This works only if there are four or fewer RX traffic classes enabled, as the SAM GMAC hardware supports screening up to four traffic classes.

CONFIG_ETH_SAM_GMAC_IRQ_PRI

IRQ priority of Ethernet device

CONFIG_ETH_SAM_GMAC_MAC0

MAC Address Byte 0

CONFIG_ETH_SAM_GMAC_MAC1

MAC Address Byte 1

CONFIG_ETH_SAM_GMAC_MAC2

MAC Address Byte 2

CONFIG_ETH_SAM_GMAC_MAC3

MAC Address Byte 3

CONFIG_ETH_SAM_GMAC_MAC4

MAC Address Byte 4

CONFIG_ETH_SAM_GMAC_MAC5

MAC Address Byte 5

CONFIG_ETH_SAM_GMAC_MAC_I2C_DEV_NAME

Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object.

CONFIG_ETH_SAM_GMAC_MAC_I2C_EEPROM

Read MAC address from an I2C EEPROM.

CONFIG_ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS

Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option.

CONFIG_ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE

Size (in bytes) of the internal EEPROM address.

CONFIG_ETH_SAM_GMAC_MAC_I2C_SLAVE_ADDRESS

I2C 7-bit address of the EEPROM chip.

CONFIG_ETH_SAM_GMAC_MAC_MANUAL

Assign an arbitrary MAC address.

CONFIG_ETH_SAM_GMAC_MII

MII

CONFIG_ETH_SAM_GMAC_NAME

Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique.

CONFIG_ETH_SAM_GMAC_PHY_ADDR

GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY transceivers. If you have a single PHY on board it is safe to leave it at 0 which is the broadcast address.

CONFIG_ETH_SAM_GMAC_QUEUES

Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority.

CONFIG_ETH_SAM_GMAC_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_SAM_GMAC_RMII

RMII

CONFIG_ETH_SMSC911X

Enable driver for SMSC/LAN911x/9220 family of chips.

CONFIG_ETH_STELLARIS

Stellaris on-board Ethernet Controller

CONFIG_ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS

Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated.

CONFIG_ETH_STM32_HAL

Enable STM32 HAL based Ethernet driver. It is available for all Ethernet enabled variants of the F2, F4 and F7 series.

CONFIG_ETH_STM32_HAL_IRQ_PRI

IRQ priority

CONFIG_ETH_STM32_HAL_MAC3

This is the byte 3 of the MAC address.

CONFIG_ETH_STM32_HAL_MAC4

This is the byte 4 of the MAC address.

CONFIG_ETH_STM32_HAL_MAC5

This is the byte 5 of the MAC address.

CONFIG_ETH_STM32_HAL_MII

Use the MII physical interface instead of RMII.

CONFIG_ETH_STM32_HAL_NAME

Device name

CONFIG_ETH_STM32_HAL_PHY_ADDRESS

The phy address to use.

CONFIG_ETH_STM32_HAL_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO

RX thread priority

CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE

RX thread stack size

CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER

When this option is activated, the buffers for DMA transfer are moved from SRAM to the DTCM (Data Tightly Coupled Memory).

CONFIG_EXCEPTIONS

This option enables support of C++ exceptions.

CONFIG_EXCEPTION_DEBUG

Install handlers for various CPU exception/trap vectors to make debugging them easier, at a small expense in code size. This prints out the specific exception vector and any associated error codes.

CONFIG_EXCEPTION_STACK_SIZE

The exception stack(s) (one per CPU) are used both for exception processing and early kernel/CPU initialization. They need only support limited call-tree depth and must fit into the low core, so they are typically smaller than the ISR stacks.

CONFIG_EXCEPTION_STACK_TRACE

If the architecture fatal handling code supports it, attempt to print a stack trace of function memory addresses when an exception is reported.

CONFIG_EXECUTE_XOR_WRITE

When enabled, will enforce that a writable page isn’t executable and vice versa. This might not be acceptable in all scenarios, so this option is given for those unafraid of shooting themselves in the foot.

If unsure, say Y.

CONFIG_EXECUTION_BENCHMARKING

This option enables the tracking of various times inside the kernel the exact set of metrics being tracked is board-dependent. All timing measurements are enabled for X86 and ARM based architectures. In other architectures only a subset is enabled.

CONFIG_EXTERNAL_LIBC

Build with external/user provided C library.

CONFIG_EXTI_STM32

Enable EXTI driver for STM32 line of MCUs

CONFIG_EXTI_STM32_EXTI0_IRQ_PRI

IRQ priority of EXTI0 interrupt

CONFIG_EXTI_STM32_EXTI10_IRQ_PRI

IRQ priority of EXTI10 interrupt

CONFIG_EXTI_STM32_EXTI11_IRQ_PRI

IRQ priority of EXTI11 interrupt

CONFIG_EXTI_STM32_EXTI12_IRQ_PRI

IRQ priority of EXTI12 interrupt

CONFIG_EXTI_STM32_EXTI13_IRQ_PRI

IRQ priority of EXTI13 interrupt

CONFIG_EXTI_STM32_EXTI14_IRQ_PRI

IRQ priority of EXTI14 interrupt

CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI

IRQ priority of EXTI15:10 interrupt

CONFIG_EXTI_STM32_EXTI15_4_IRQ_PRI

IRQ priority of EXTI15:4 interrupt

CONFIG_EXTI_STM32_EXTI15_IRQ_PRI

IRQ priority of EXTI15 interrupt

CONFIG_EXTI_STM32_EXTI1_0_IRQ_PRI

IRQ priority of EXTI1:0 interrupt

CONFIG_EXTI_STM32_EXTI1_IRQ_PRI

IRQ priority of EXTI1 interrupt

CONFIG_EXTI_STM32_EXTI2_IRQ_PRI

IRQ priority of EXTI2 interrupt

CONFIG_EXTI_STM32_EXTI3_2_IRQ_PRI

IRQ priority of EXTI3:2 interrupt

CONFIG_EXTI_STM32_EXTI3_IRQ_PRI

IRQ priority of EXTI3 interrupt

CONFIG_EXTI_STM32_EXTI4_IRQ_PRI

IRQ priority of EXTI4 interrupt

CONFIG_EXTI_STM32_EXTI5_IRQ_PRI

IRQ priority of EXTI5 interrupt

CONFIG_EXTI_STM32_EXTI6_IRQ_PRI

IRQ priority of EXTI6 interrupt

CONFIG_EXTI_STM32_EXTI7_IRQ_PRI

IRQ priority of EXTI7 interrupt

CONFIG_EXTI_STM32_EXTI8_IRQ_PRI

IRQ priority of EXTI8 interrupt

CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI

IRQ priority of EXTI9:5 interrupt

CONFIG_EXTI_STM32_EXTI9_IRQ_PRI

IRQ priority of EXTI9 interrupt

CONFIG_EXTI_STM32_LPTIM1_IRQ_PRI

IRQ priority of LPTIM1 interrupt

CONFIG_EXTI_STM32_OTG_FS_WKUP_IRQ_PRI

IRQ priority of USB OTG FS Wake interrupt

CONFIG_EXTI_STM32_PVD_IRQ_PRI

IRQ priority of RVD Through interrupt

CONFIG_EXTI_STM32_RTC_WKUP_IRQ_PRI

IRQ priority of RTC Wake Up interrupt

CONFIG_EXTI_STM32_TAMP_STAMP_IRQ_PRI

IRQ priority of Tamper and Timestamp interrupt

CONFIG_EXTRA_EXCEPTION_INFO

Have exceptions print additional useful debugging information in human-readable form, at the expense of code size. For example, the cause code for an exception will be supplemented by a string describing what that cause code means.

CONFIG_FAKE_ENTROPY_NATIVE_POSIX

This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed.

CONFIG_FAT_FILESYSTEM_ELM

Use the ELM FAT File system implementation.

CONFIG_FAULT_DUMP

Different levels for display information when a fault occurs.

2: The default. Display specific and verbose information. Consumes

the most memory (long strings).

1: Display general and short information. Consumes less memory

(short strings).

0: Off.

CONFIG_FCB

Enable support of Flash Circular Buffer.

CONFIG_FILE_SYSTEM

Enables support for file system.

CONFIG_FILE_SYSTEM_LITTLEFS

Enables LittleFS file system support.

CONFIG_FILE_SYSTEM_NFFS

Enables NFFS file system support. Note: NFFS requires 1-byte unaligned access to flash thus it will not work on devices that support only aligned flash access.

CONFIG_FILE_SYSTEM_SHELL

This shell provides basic browsing of the contents of the file system.

CONFIG_FLASH

Enable support for the flash hardware.

CONFIG_FLASH_BASE_ADDRESS

This option specifies the base address of the flash on the board. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration.

CONFIG_FLASH_HAS_DRIVER_ENABLED

This option is enabled when any flash driver is enabled.

CONFIG_FLASH_HAS_PAGE_LAYOUT

This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages.

CONFIG_FLASH_LOAD_OFFSET

This option specifies the byte offset from the beginning of flash that the kernel should be loaded into. Changing this value from zero will affect the Zephyr image’s link, and will decrease the total amount of flash available for use by application code.

If unsure, leave at the default value 0.

CONFIG_FLASH_LOAD_SIZE

If non-zero, this option specifies the size, in bytes, of the flash area that the Zephyr image will be allowed to occupy. If zero, the image will be able to occupy from the FLASH_LOAD_OFFSET to the end of the device.

If unsure, leave at the default value 0.

CONFIG_FLASH_LOG_LEVEL

CONFIG_FLASH_LOG_LEVEL_DBG

Debug

CONFIG_FLASH_LOG_LEVEL_ERR

Error

CONFIG_FLASH_LOG_LEVEL_INF

Info

CONFIG_FLASH_LOG_LEVEL_OFF

Off

CONFIG_FLASH_LOG_LEVEL_WRN

Warning

CONFIG_FLASH_MAP

Enable support of flash map abstraction.

CONFIG_FLASH_MAP_CUSTOM

This option enables custom flash map description. User must provide such a description in place of default on if had enabled this option.

CONFIG_FLASH_MAP_SHELL

This enables shell commands to list and test flash maps.

CONFIG_FLASH_NATIVE_POSIX

Enable Native POSIX flash driver.

CONFIG_FLASH_NATIVE_POSIX_SECTOR_SIZE

This option specifies the sector size of the Native POSIX flash in KB

CONFIG_FLASH_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the flash driver.

CONFIG_FLASH_PAGE_LAYOUT

Enables API for retrieving the layout of flash memory pages.

CONFIG_FLASH_SHELL

Enable the flash shell with flash related commands such as test, write, read and erase.

CONFIG_FLASH_SIMULATOR

Enable the flash simulator.

CONFIG_FLASH_SIMULATOR_DOUBLE_WRITES

If selected, writing to a non-erased program unit will succeed, otherwise, it will return an error. Keep in mind that write operations can only pull bits to zero, regardless.

CONFIG_FLASH_SIMULATOR_ERASE_PROTECT

If selected, turning on write protection will also prevent erasing.

CONFIG_FLASH_SIMULATOR_MIN_ERASE_TIME_US

Minimum erase time (µS)

CONFIG_FLASH_SIMULATOR_MIN_READ_TIME_US

Minimum read time (µS)

CONFIG_FLASH_SIMULATOR_MIN_WRITE_TIME_US

Minimum write time (µS)

CONFIG_FLASH_SIMULATOR_SIMULATE_TIMING

Enable hardware timing simulation

CONFIG_FLASH_SIMULATOR_STAT_PAGE_COUNT

Only up to this number of beginning pages will be tracked while catching dedicated flash operations and thresholds. This number is not automatic because implementation uses UNTIL_REPEAT() macro, which is limited to take explicitly number of iterations. This is why it’s not possible to calculate the number of pages with preprocessor using DT properties.

CONFIG_FLASH_SIMULATOR_UNALIGNED_READ

If selected, the reading operation does not check if access is aligned. Disable this option only if you want to simulate a specific FLASH interface that requires aligned read access.

CONFIG_FLASH_SIZE

This option specifies the size of the flash in kB. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration.

CONFIG_FLEXPWM1_PWM0

Enable output for FLEXPWM1_PWM0 in the driver. Say y here if you want to use FLEXPWM1_PWM0 output.

CONFIG_FLEXPWM1_PWM1

Enable output for FLEXPWM1_PWM1 in the driver. Say y here if you want to use FLEXPWM1_PWM1 output.

CONFIG_FLEXPWM1_PWM2

Enable output for FLEXPWM1_PWM2 in the driver. Say y here if you want to use FLEXPWM1_PWM2 output.

CONFIG_FLEXPWM1_PWM3

Enable output for FLEXPWM1_PWM3 in the driver. Say y here if you want to use FLEXPWM1_PWM3 output.

CONFIG_FLEXPWM2_PWM0

Enable output for FLEXPWM2_PWM0 in the driver. Say y here if you want to use FLEXPWM2_PWM0 output.

CONFIG_FLEXPWM2_PWM1

Enable output for FLEXPWM2_PWM1 in the driver. Say y here if you want to use FLEXPWM2_PWM1 output.

CONFIG_FLEXPWM2_PWM2

Enable output for FLEXPWM2_PWM2 in the driver. Say y here if you want to use FLEXPWM2_PWM2 output.

CONFIG_FLEXPWM2_PWM3

Enable output for FLEXPWM2_PWM3 in the driver. Say y here if you want to use FLEXPWM2_PWM3 output.

CONFIG_FLEXPWM3_PWM0

Enable output for FLEXPWM3_PWM0 in the driver. Say y here if you want to use FLEXPWM3_PWM0 output.

CONFIG_FLEXPWM3_PWM1

Enable output for FLEXPWM3_PWM1 in the driver. Say y here if you want to use FLEXPWM3_PWM1 output.

CONFIG_FLEXPWM3_PWM2

Enable output for FLEXPWM3_PWM2 in the driver. Say y here if you want to use FLEXPWM3_PWM2 output.

CONFIG_FLEXPWM3_PWM3

Enable output for FLEXPWM3_PWM3 in the driver. Say y here if you want to use FLEXPWM3_PWM3 output.

CONFIG_FLEXPWM4_PWM0

Enable output for FLEXPWM4_PWM0 in the driver. Say y here if you want to use FLEXPWM4_PWM0 output.

CONFIG_FLEXPWM4_PWM1

Enable output for FLEXPWM4_PWM1 in the driver. Say y here if you want to use FLEXPWM4_PWM1 output.

CONFIG_FLEXPWM4_PWM2

Enable output for FLEXPWM4_PWM2 in the driver. Say y here if you want to use FLEXPWM4_PWM2 output.

CONFIG_FLEXPWM4_PWM3

Enable output for FLEXPWM4_PWM3 in the driver. Say y here if you want to use FLEXPWM4_PWM3 output.

CONFIG_FLOAT

This option allows threads to use the floating point registers. By default, only a single thread may use the registers.

Disabling this option means that any thread that uses a floating point register will get a fatal exception.

CONFIG_FNMATCH

This option enables the fnmatch library

CONFIG_FORCE_NO_ASSERT

This boolean option disables Zephyr assertion testing even in circumstances (sanitycheck) where it is enabled via CFLAGS and not Kconfig. Added solely to be able to work around compiler bugs for specific tests.

CONFIG_FP_FPU_DA

CONFIG_FP_HARDABI

This option selects the Floating point ABI in which hardware floating point instructions are generated and uses FPU-specific calling conventions

CONFIG_FP_SHARING

This option allows multiple threads to use the floating point registers.

CONFIG_FP_SOFTABI

This option selects the Floating point ABI in which hardware floating point instructions are generated but soft-float calling conventions.

CONFIG_FRAMEBUF_DISPLAY

Enable framebuffer-based display ‘helper’ driver.

CONFIG_FS_FATFS_NUM_DIRS

Maximum number of opened directories

CONFIG_FS_FATFS_NUM_FILES

Maximum number of opened files

CONFIG_FS_LITTLEFS_BLOCK_CYCLES

For dynamic wear leveling, the number of erase cycles before data is moved to another block. Set to a non-positive value to disable leveling.

CONFIG_FS_LITTLEFS_CACHE_SIZE

Each cache buffers a portion of a block in RAM. The littlefs needs a read cache, a program cache, and one additional cache per file. Larger caches can improve performance by storing more data and reducing the number of disk accesses. Must be a multiple of the read and program sizes of the underlying flash device, and a factor of the block size.

CONFIG_FS_LITTLEFS_FC_MEM_POOL

littlefs requires a per-file buffer to cache data. For applications that use the default configuration parameters a memory slab is reserved to support up to FS_LITTLE_FS_NUM_FILES blocks of FS_LITTLEFS_CACHE_SIZE bytes.

When applications customize littlefs configurations and support different cache sizes for different partitions this preallocation is inadequate.

Select this feature to enable a memory pool allocator for littlefs file caches.

CONFIG_FS_LITTLEFS_FC_MEM_POOL_MAX_SIZE

Maximum block size for littlefs file cache memory pool

CONFIG_FS_LITTLEFS_FC_MEM_POOL_MIN_SIZE

Minimum block size for littlefs file cache memory pool

CONFIG_FS_LITTLEFS_FC_MEM_POOL_NUM_BLOCKS

Number of maximum sized blocks in littlefs file cache memory pool

CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE

A larger lookahead buffer increases the number of blocks found during an allocation pass. The lookahead buffer is stored as a compact bitmap, so each byte of RAM can track 8 blocks. Must be a multiple of 8.

CONFIG_FS_LITTLEFS_NUM_DIRS

This is a global maximum across all mounted littlefs filesystems.

CONFIG_FS_LITTLEFS_NUM_FILES

This is a global maximum across all mounted littlefs filesystems.

CONFIG_FS_LITTLEFS_PROG_SIZE

All program operations will be a multiple of this value.

CONFIG_FS_LITTLEFS_READ_SIZE

All read operations will be a multiple of this value.

CONFIG_FS_LOG_LEVEL

CONFIG_FS_LOG_LEVEL_DBG

Debug

CONFIG_FS_LOG_LEVEL_ERR

Error

CONFIG_FS_LOG_LEVEL_INF

Info

CONFIG_FS_LOG_LEVEL_OFF

Off

CONFIG_FS_LOG_LEVEL_WRN

Warning

CONFIG_FS_MGMT_DL_CHUNK_SIZE

Limits the maximum chunk size for file downloads, in bytes. A buffer of this size gets allocated on the stack during handling of a file download command.

CONFIG_FS_MGMT_PATH_SIZE

Limits the maximum path length for file operations, in bytes. A buffer of this size gets allocated on the stack during handling of file upload and download commands.

CONFIG_FS_MGMT_UL_CHUNK_SIZE

Limits the maximum chunk size for file uploads, in bytes. A buffer of this size gets allocated on the stack during handling of a file upload command.

CONFIG_FS_NFFS_FLASH_DEV_NAME

Flash device name to be used

CONFIG_FS_NFFS_NUM_BLOCKS

Maximum number of blocks

CONFIG_FS_NFFS_NUM_CACHE_BLOCKS

Number of cached blocks

CONFIG_FS_NFFS_NUM_CACHE_INODES

Number of cached files’ inodes

CONFIG_FS_NFFS_NUM_DIRS

Maximum number of opened directories

CONFIG_FS_NFFS_NUM_FILES

Maximum number of opened files

CONFIG_FS_NFFS_NUM_INODES

Maximum number of inodes

CONFIG_FUSE_FS_ACCESS

Expose file system partitions to the host system through FUSE.

CONFIG_FXAS21002

Enable driver for the FXAS21002 gyroscope

CONFIG_FXAS21002_DR

Selects the output data rate 0: 800 Hz 1: 400 Hz 2: 200 Hz 3: 100 Hz 4: 50 Hz 5: 25 Hz 6: 12.5 Hz 7: 12.5 Hz

CONFIG_FXAS21002_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXAS21002_RANGE

Selects the full scale range 0: +/-2000 dps (62.5 mdps/LSB) 1: +/-1000 dps (31.25 mdps/LSB) 2: +/-500 dps (15.625 mdps/LSB) 3: +/-250 dps (7.8125 mdps/LSB)

CONFIG_FXAS21002_THREAD_PRIORITY

Own thread priority

CONFIG_FXAS21002_THREAD_STACK_SIZE

Own thread stack size

CONFIG_FXAS21002_TRIGGER

CONFIG_FXAS21002_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_FXAS21002_TRIGGER_NONE

No trigger

CONFIG_FXAS21002_TRIGGER_OWN_THREAD

Use own thread

CONFIG_FXAS21002_WHOAMI

The datasheet defines the value of the WHOAMI register, but some pre-production devices can have a different value. It is unlikely you should need to change this configuration option from the default.

CONFIG_FXOS8700

Enable driver for the FXOS8700 accelerometer/magnetometer. The driver also supports MMA8451Q, MMA8652FC and MMA8653FC accelerometers. If the driver is used with one of these accelerometers then the Accelerometer-only mode should be selected.”

CONFIG_FXOS8700_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_MODE_ACCEL

Accelerometer-only mode

CONFIG_FXOS8700_MODE_HYBRID

Hybrid (accel+mag) mode

CONFIG_FXOS8700_MODE_MAGN

Magnetometer-only mode

CONFIG_FXOS8700_MOTION

Enable motion detection

CONFIG_FXOS8700_MOTION_INT1

Say Y to route motion interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_PM_HIGH_RESOLUTION

High resolution power mode

CONFIG_FXOS8700_PM_LOW_NOISE_LOW_POWER

Low noise low power mode

CONFIG_FXOS8700_PM_LOW_POWER

Low power mode

CONFIG_FXOS8700_PM_NORMAL

Normal power mode

CONFIG_FXOS8700_PULSE

Enable pulse detection

CONFIG_FXOS8700_PULSE_CFG

Pulse configuration register

CONFIG_FXOS8700_PULSE_INT1

Say Y to route pulse interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_PULSE_LTCY

The time interval that starts after the first pulse detection where the pulse-detection function ignores the start of a new pulse. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.

CONFIG_FXOS8700_PULSE_THSX

Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_THSY

Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_THSZ

Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_TMLT

The maximum time interval that can elapse between the start of the acceleration on the selected channel exceeding the specified threshold and the end when the channel acceleration goes back below the specified threshold. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB.

CONFIG_FXOS8700_PULSE_WIND

The maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The detected second pulse width must be shorter than the time limit constraint specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.

CONFIG_FXOS8700_RANGE_2G

2g (0.244 mg/LSB)

CONFIG_FXOS8700_RANGE_4G

4g (0.488 mg/LSB)

CONFIG_FXOS8700_RANGE_8G

8g (0.976 mg/LSB)

CONFIG_FXOS8700_TEMP

Enable the temperature sensor. Note that the temperature sensor is uncalibrated and its output for a given temperature may vary from one device to the next.

CONFIG_FXOS8700_THREAD_PRIORITY

Own thread priority

CONFIG_FXOS8700_THREAD_STACK_SIZE

Own thread stack size

CONFIG_FXOS8700_TRIGGER

CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_FXOS8700_TRIGGER_NONE

No trigger

CONFIG_FXOS8700_TRIGGER_OWN_THREAD

Use own thread

CONFIG_GDT_DYNAMIC

This option stores the GDT in RAM instead of ROM, so that it may be modified at runtime at the expense of some memory.

CONFIG_GEN_IRQ_START_VECTOR

On some architectures, part of the vector table may be reserved for system exceptions and is declared separately from the tables created by gen_isr_tables.py. When creating these tables, this value will be subtracted from CONFIG_NUM_IRQS to properly size them. This is a hidden option which needs to be set per architecture and left alone.

CONFIG_GEN_IRQ_VECTOR_TABLE

This option controls whether a platform using gen_isr_tables needs an interrupt vector table created. Only disable this if the platform does not use a vector table at all, or requires the vector table to be in a format that is not an array of function pointers indexed by IRQ line. In the latter case, the vector table must be supplied by the application or architecture code.

CONFIG_GEN_ISR_TABLES

This option controls whether a platform uses the gen_isr_tables script to generate its interrupt tables. This mechanism will create an appropriate hardware vector table and/or software IRQ table.

CONFIG_GEN_SW_ISR_TABLE

This option controls whether a platform using gen_isr_tables needs a software ISR table table created. This is an array of struct _isr_table_entry containing the interrupt service routine and supplied parameter.

CONFIG_GIC

The ARM Generic Interrupt Controller works with Cortex-A and Cortex-R processors.

CONFIG_GPIO

Include GPIO drivers in system config

CONFIG_GPIO_AS_PINRESET

GPIO as pin reset (reset button)

CONFIG_GPIO_A_STELLARIS

Enable GPIO port A support

CONFIG_GPIO_B_STELLARIS

Enable GPIO port B support

CONFIG_GPIO_CC13XX_CC26XX

Enable the TI SimpleLink CC13xx / CC26xx GPIO driver.

CONFIG_GPIO_CC2650

Enable the GPIO driver on boards equipped with TI CC2650.

CONFIG_GPIO_CC2650_INIT_PRIO

GPIO driver initialization priority.

CONFIG_GPIO_CC2650_NAME

GPIO driver name.

CONFIG_GPIO_CC32XX

Enable the GPIO driver on TI SimpleLink CC32xx boards

CONFIG_GPIO_CC32XX_A0

Include support for the GPIO port A0.

CONFIG_GPIO_CC32XX_A1

Include support for the GPIO port A1.

CONFIG_GPIO_CC32XX_A2

Include support for the GPIO port A2.

CONFIG_GPIO_CC32XX_A3

Include support for the GPIO port A3.

CONFIG_GPIO_CMSDK_AHB

Enable config options to support the ARM CMSDK GPIO controllers.

Says n if not sure.

CONFIG_GPIO_CMSDK_AHB_PORT0

Build the driver to utilize GPIO controller Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME

Device name for Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI

Interrupt priority for Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT1

Build the driver to utilize GPIO controller Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME

Device name for Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI

Interrupt priority for Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT2

Build the driver to utilize GPIO controller Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME

Device name for Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI

Interrupt priority for Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT3

Build the driver to utilize GPIO controller Port 3.

CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME

Device name for Port 3.

CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI

Interrupt priority for Port 3.

CONFIG_GPIO_C_STELLARIS

Enable GPIO port C support

CONFIG_GPIO_DW

Enable driver for Designware GPIO

CONFIG_GPIO_DW_0

Include Designware GPIO driver

CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_0_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_0_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_0_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_0_NAME

Driver name

CONFIG_GPIO_DW_1

Include Designware GPIO driver

CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_1_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_1_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_1_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_1_NAME

Driver name

CONFIG_GPIO_DW_2

Include Designware GPIO driver

CONFIG_GPIO_DW_2_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_2_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_2_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_2_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_2_NAME

Driver name

CONFIG_GPIO_DW_3

Include Designware GPIO driver

CONFIG_GPIO_DW_3_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_3_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_3_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_3_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_3_NAME

Driver name

CONFIG_GPIO_DW_CLOCK_GATE

Enable clock gating

CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME

CONFIG_GPIO_DW_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_DW_SHARED_IRQ

CONFIG_GPIO_D_STELLARIS

Enable GPIO port D support

CONFIG_GPIO_ESP32

Enables the ESP32 GPIO driver

CONFIG_GPIO_ESP32_0

Include support for GPIO pins 0-31 on the ESP32.

CONFIG_GPIO_ESP32_1

Include support for GPIO pins 32-39 on the ESP32.

CONFIG_GPIO_ESP32_IRQ

IRQ line for ESP32 GPIO pins

CONFIG_GPIO_E_STELLARIS

Enable GPIO port E support

CONFIG_GPIO_F_STELLARIS

Enable GPIO port F support

CONFIG_GPIO_GECKO

Enable the Gecko gpio driver.

CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY

Common initialization priority

CONFIG_GPIO_GECKO_PORTA

Enable Port A.

CONFIG_GPIO_GECKO_PORTB

Enable Port B.

CONFIG_GPIO_GECKO_PORTC

Enable Port C.

CONFIG_GPIO_GECKO_PORTD

Enable Port D.

CONFIG_GPIO_GECKO_PORTE

Enable Port E.

CONFIG_GPIO_GECKO_PORTF

Enable Port F.

CONFIG_GPIO_GECKO_PORTG

Enable Port G.

CONFIG_GPIO_GECKO_PORTH

Enable Port H.

CONFIG_GPIO_GECKO_PORTI

Enable Port I.

CONFIG_GPIO_GECKO_PORTJ

Enable Port J.

CONFIG_GPIO_GECKO_PORTK

Enable Port K.

CONFIG_GPIO_G_STELLARIS

Enable GPIO port G support

CONFIG_GPIO_HT16K33

Enable keyscan driver for HT16K33.

The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports matrix key scan circuit of up to 13x3 keys.

The keyscan functionality is exposed as up to 3 GPIO controller drivers, each supporting GPIO callbacks for keyscan event notifications.

CONFIG_GPIO_HT16K33_INIT_PRIORITY

Device driver initialization priority. This driver must be initialized after the HT16K33 LED driver.

CONFIG_GPIO_IMX

Enable the IMX GPIO driver.

CONFIG_GPIO_IMX_PORT_1

Enable Port 1.

CONFIG_GPIO_IMX_PORT_2

Enable Port 2.

CONFIG_GPIO_IMX_PORT_3

Enable Port 3.

CONFIG_GPIO_IMX_PORT_4

Enable Port 4.

CONFIG_GPIO_IMX_PORT_5

Enable Port 5.

CONFIG_GPIO_IMX_PORT_6

Enable Port 6.

CONFIG_GPIO_IMX_PORT_7

Enable Port 7.

CONFIG_GPIO_INTEL_APL

Enable driver for Intel Apollo Lake SoC GPIO

CONFIG_GPIO_INTEL_APL_CHECK_PERMS

This option enables the checks to make sure the GPIO pin can be manipulated. Only if the pin is owned by the host software and its functioning as GPIO, then the driver allows manipulating the pin.

Say y if unsure.

CONFIG_GPIO_LOG_LEVEL

CONFIG_GPIO_LOG_LEVEL_DBG

Debug

CONFIG_GPIO_LOG_LEVEL_ERR

Error

CONFIG_GPIO_LOG_LEVEL_INF

Info

CONFIG_GPIO_LOG_LEVEL_OFF

Off

CONFIG_GPIO_LOG_LEVEL_WRN

Warning

CONFIG_GPIO_MCUX

Enable the MCUX pinmux driver.

CONFIG_GPIO_MCUX_IGPIO

Enable the MCUX IGPIO driver.

CONFIG_GPIO_MCUX_IGPIO_1

Enable Port 1.

CONFIG_GPIO_MCUX_IGPIO_2

Enable Port 2.

CONFIG_GPIO_MCUX_IGPIO_3

Enable Port 3.

CONFIG_GPIO_MCUX_IGPIO_4

Enable Port 4.

CONFIG_GPIO_MCUX_IGPIO_5

Enable Port 5.

CONFIG_GPIO_MCUX_LPC

Enable the MCUX LPC pinmux driver.

CONFIG_GPIO_MCUX_LPC_PORT0

Enable Port 0.

CONFIG_GPIO_MCUX_LPC_PORT0_NAME

Port 0 driver name

CONFIG_GPIO_MCUX_LPC_PORT1

Enable Port 1.

CONFIG_GPIO_MCUX_LPC_PORT1_NAME

Port 1 driver name

CONFIG_GPIO_MCUX_PORTA

Enable Port A.

CONFIG_GPIO_MCUX_PORTB

Enable Port B.

CONFIG_GPIO_MCUX_PORTC

Enable Port C.

CONFIG_GPIO_MCUX_PORTD

Enable Port D.

CONFIG_GPIO_MCUX_PORTE

Enable Port E.

CONFIG_GPIO_MMIO32

This is a driver for accessing a simple, fixed purpose, 32-bit memory-mapped i/o register using the same APIs as GPIO drivers. This is useful when an SoC or board has registers that aren’t part of a GPIO IP block and these registers are used to control things that Zephyr normally expects to be specified using a GPIO pin, e.g. for driving an LED, or chip-select line for an SPI device.

CONFIG_GPIO_NRFX

Enable GPIO driver for nRF line of MCUs.

CONFIG_GPIO_NRF_INIT_PRIORITY

Initialization priority for nRF GPIO.

CONFIG_GPIO_NRF_P0

Enable nRF GPIO port P0 config options.

CONFIG_GPIO_NRF_P1

Enable nRF GPIO port P1 config options.

CONFIG_GPIO_PCAL9535A

Enable driver for PCAL9535A I2C-based GPIO chip.

CONFIG_GPIO_PCAL9535A_0

Enable config options for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #0 is binded.

CONFIG_GPIO_PCAL9535A_1

Enable config options for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #1 is binded.

CONFIG_GPIO_PCAL9535A_2

Enable config options for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #2 is binded.

CONFIG_GPIO_PCAL9535A_3

Enable config options for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #3 is binded.

CONFIG_GPIO_PCAL9535A_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_RV32M1

Enable the RV32M1 GPIO driver.

CONFIG_GPIO_RV32M1_PORTA

Enable Port A.

CONFIG_GPIO_RV32M1_PORTB

Enable Port B.

CONFIG_GPIO_RV32M1_PORTC

Enable Port C.

CONFIG_GPIO_RV32M1_PORTD

Enable Port D.

CONFIG_GPIO_RV32M1_PORTE

Enable Port E.

CONFIG_GPIO_SAM

Enable support for the Atmel SAM ‘PORT’ GPIO controllers.

CONFIG_GPIO_SAM0

Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers.

CONFIG_GPIO_SHELL

Enable GPIO Shell for testing.

CONFIG_GPIO_SIFIVE

Enable driver for the SiFive Freedom GPIO controller.

Says n if not sure.

CONFIG_GPIO_SIFIVE_0_PRIORITY

GPIO 0 interrupt priority

CONFIG_GPIO_SIFIVE_10_PRIORITY

GPIO 10 interrupt priority

CONFIG_GPIO_SIFIVE_11_PRIORITY

GPIO 11 interrupt priority

CONFIG_GPIO_SIFIVE_12_PRIORITY

GPIO 12 interrupt priority

CONFIG_GPIO_SIFIVE_13_PRIORITY

GPIO 13 interrupt priority

CONFIG_GPIO_SIFIVE_14_PRIORITY

GPIO 14 interrupt priority

CONFIG_GPIO_SIFIVE_15_PRIORITY

GPIO 15 interrupt priority

CONFIG_GPIO_SIFIVE_16_PRIORITY

GPIO 16 interrupt priority

CONFIG_GPIO_SIFIVE_17_PRIORITY

GPIO 17 interrupt priority

CONFIG_GPIO_SIFIVE_18_PRIORITY

GPIO 18 interrupt priority

CONFIG_GPIO_SIFIVE_19_PRIORITY

GPIO 19 interrupt priority

CONFIG_GPIO_SIFIVE_1_PRIORITY

GPIO 1 interrupt priority

CONFIG_GPIO_SIFIVE_20_PRIORITY

GPIO 20 interrupt priority

CONFIG_GPIO_SIFIVE_21_PRIORITY

GPIO 21 interrupt priority

CONFIG_GPIO_SIFIVE_22_PRIORITY

GPIO 22 interrupt priority

CONFIG_GPIO_SIFIVE_23_PRIORITY

GPIO 23 interrupt priority

CONFIG_GPIO_SIFIVE_24_PRIORITY

GPIO 24 interrupt priority

CONFIG_GPIO_SIFIVE_25_PRIORITY

GPIO 25 interrupt priority

CONFIG_GPIO_SIFIVE_26_PRIORITY

GPIO 26 interrupt priority

CONFIG_GPIO_SIFIVE_27_PRIORITY

GPIO 27 interrupt priority

CONFIG_GPIO_SIFIVE_28_PRIORITY

GPIO 28 interrupt priority

CONFIG_GPIO_SIFIVE_29_PRIORITY

GPIO 29 interrupt priority

CONFIG_GPIO_SIFIVE_2_PRIORITY

GPIO 2 interrupt priority

CONFIG_GPIO_SIFIVE_30_PRIORITY

GPIO 30 interrupt priority

CONFIG_GPIO_SIFIVE_31_PRIORITY

GPIO 31 interrupt priority

CONFIG_GPIO_SIFIVE_3_PRIORITY

GPIO 3 interrupt priority

CONFIG_GPIO_SIFIVE_4_PRIORITY

GPIO 4 interrupt priority

CONFIG_GPIO_SIFIVE_5_PRIORITY

GPIO 5 interrupt priority

CONFIG_GPIO_SIFIVE_6_PRIORITY

GPIO 6 interrupt priority

CONFIG_GPIO_SIFIVE_7_PRIORITY

GPIO 7 interrupt priority

CONFIG_GPIO_SIFIVE_8_PRIORITY

GPIO 8 interrupt priority

CONFIG_GPIO_SIFIVE_9_PRIORITY

GPIO 9 interrupt priority

CONFIG_GPIO_STELLARIS

Enable support for the Stellaris GPIO controllers.

CONFIG_GPIO_STM32

Enable GPIO driver for STM32 line of MCUs

CONFIG_GPIO_STM32_PORTA

Enable GPIO port A support

CONFIG_GPIO_STM32_PORTB

Enable GPIO port B support

CONFIG_GPIO_STM32_PORTC

Enable GPIO port C support

CONFIG_GPIO_STM32_PORTD

Enable GPIO port D support

CONFIG_GPIO_STM32_PORTE

Enable GPIO port E support

CONFIG_GPIO_STM32_PORTF

Enable GPIO port F support

CONFIG_GPIO_STM32_PORTG

Enable GPIO port G support

CONFIG_GPIO_STM32_PORTH

Enable GPIO port H support

CONFIG_GPIO_STM32_PORTI

Enable GPIO port I support

CONFIG_GPIO_STM32_PORTJ

Enable GPIO port J support

CONFIG_GPIO_STM32_PORTK

Enable GPIO port K support

CONFIG_GPIO_STM32_SWJ_DISABLE

JTAG-DP Disabled and SW-DP Disabled

CONFIG_GPIO_STM32_SWJ_ENABLE

Full SWJ (JTAG-DP + SW-DP): Reset State

CONFIG_GPIO_STM32_SWJ_NOJTAG

JTAG-DP Disabled and SW-DP Enabled

CONFIG_GPIO_STM32_SWJ_NONJTRST

Full SWJ (JTAG-DP + SW-DP) but without NJTRST

CONFIG_GPIO_SX1509B

Enable driver for SX1509B I2C GPIO chip.

CONFIG_GPIO_SX1509B_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_XEC

Enable the Microchip XEC gpio driver.

CONFIG_GPIO_XEC_GPIO000_036

Enable GPIO 000-036 or what would be equivalent to PortA.

CONFIG_GPIO_XEC_GPIO040_076

Enable GPIO 040-076 or what would be equivalent to Port B

CONFIG_GPIO_XEC_GPIO100_136

Enable GPIO 100-136 or what would be equivalent to Port C

CONFIG_GPIO_XEC_GPIO140_176

Enable GPIO 140-176 or what would be equivalent to Port C

CONFIG_GPIO_XEC_GPIO200_236

Enable GPIO 200-236 or what would be equivalent to Port D

CONFIG_GPIO_XEC_GPIO240_276

Enable GPIO 240-276 or what would be equivalent to Port E

CONFIG_GP_ALL_DATA

Use GP relative access for all data in the program, not just small data. Use this if your board has 64K or less of RAM.

CONFIG_GP_GLOBAL

Use global pointer relative offsets for small globals declared anywhere in the executable. Note that if any small globals that are put in alternate sections they must be declared in headers with proper __attribute__((section)) or the linker will error out.

CONFIG_GP_LOCAL

Use global pointer relative offsets for small globals declared in the same C file as the code that uses it.

CONFIG_GP_NONE

Do not use global pointer relative offsets at all

CONFIG_GROVE_LCD_RGB

Setting this value will enable driver support for the Groove-LCD RGB Backlight.

CONFIG_GROVE_LCD_RGB_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which the Grove LCD is connected.

CONFIG_GROVE_LIGHT_SENSOR

Setting this value will enable driver support for the Grove Light Sensor.

CONFIG_GROVE_LIGHT_SENSOR_ADC_CHANNEL

Specify the channel of the ADC to which the Grove Light Sensor is connected.

CONFIG_GROVE_LIGHT_SENSOR_ADC_DEV_NAME

Specify the device name of the ADC to which the Grove Light Sensor is connected.

CONFIG_GROVE_LIGHT_SENSOR_NAME

Specify the device name with which the sensor is identified.

CONFIG_GROVE_TEMPERATURE_SENSOR

Setting this value will enable driver support for the Grove Temperature Sensor.

CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_CHANNEL

Specify the channel of the ADC to which the Grove Temperature Sensor is connected.

CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_DEV_NAME

Specify the device name of the ADC to which the Grove Temperature Sensor is connected.

CONFIG_GROVE_TEMPERATURE_SENSOR_NAME

Specify the device name with which the Grove Temperature Sensor is identified.

CONFIG_GROVE_TEMPERATURE_SENSOR_V1_0

Version 1.0

CONFIG_GROVE_TEMPERATURE_SENSOR_V1_X

Version 1.1 or 1.2

CONFIG_HARDWARE_DEVICE_CS_GENERATOR

Enables a cryptographically secure random number generator that uses the enabled hardware random number driver to generate random numbers.

CONFIG_HARVARD

The ARC CPU can be configured to have two busses; one for instruction fetching and another that serves as a data bus.

CONFIG_HAS_ALTERA_HAL

Altera HAL drivers support

CONFIG_HAS_CC13X2_CC26X2_SDK

CONFIG_HAS_CC3220SDK

CONFIG_HAS_CMSIS_CORE

CONFIG_HAS_CMSIS_CORE_M

CONFIG_HAS_CMSIS_CORE_R

CONFIG_HAS_COVERAGE_SUPPORT

The code coverage report generation is only available on boards with enough spare RAM to buffer the coverage data, or on boards based on the POSIX ARCH.

CONFIG_HAS_CYPRESS_DRIVERS

CONFIG_HAS_DIV_INSTRUCTION

CONFIG_HAS_DTS

This option specifies that the target platform supports device tree configuration.

CONFIG_HAS_DTS_ENTROPY

This option specifies that the target platform supports device tree configuration for entropy/random number.

CONFIG_HAS_DTS_GPIO

This option specifies that the target platform supports device tree configuration for GPIO.

CONFIG_HAS_DTS_I2C

This option specifies that the target platform supports device tree configuration for I2c.

CONFIG_HAS_DTS_WDT

This option specifies that the target platform supports device tree configuration for WDT.

CONFIG_HAS_FLASH_LOAD_OFFSET

This option is selected by targets having a FLASH_LOAD_OFFSET and FLASH_LOAD_SIZE.

CONFIG_HAS_HW_NRF_ACL

CONFIG_HAS_HW_NRF_ADC

CONFIG_HAS_HW_NRF_BPROT

CONFIG_HAS_HW_NRF_CC310

CONFIG_HAS_HW_NRF_CC312

CONFIG_HAS_HW_NRF_CCM

CONFIG_HAS_HW_NRF_CLOCK

CONFIG_HAS_HW_NRF_COMP

CONFIG_HAS_HW_NRF_DPPIC

CONFIG_HAS_HW_NRF_ECB

CONFIG_HAS_HW_NRF_EGU0

CONFIG_HAS_HW_NRF_EGU1

CONFIG_HAS_HW_NRF_EGU2

CONFIG_HAS_HW_NRF_EGU3

CONFIG_HAS_HW_NRF_EGU4

CONFIG_HAS_HW_NRF_EGU5

CONFIG_HAS_HW_NRF_GPIO0

CONFIG_HAS_HW_NRF_GPIO1

CONFIG_HAS_HW_NRF_GPIOTE

CONFIG_HAS_HW_NRF_I2S

CONFIG_HAS_HW_NRF_IPC

CONFIG_HAS_HW_NRF_LPCOMP

CONFIG_HAS_HW_NRF_MPU

CONFIG_HAS_HW_NRF_MWU

CONFIG_HAS_HW_NRF_NFCT

CONFIG_HAS_HW_NRF_PDM

CONFIG_HAS_HW_NRF_POWER

CONFIG_HAS_HW_NRF_PPI

CONFIG_HAS_HW_NRF_PWM0

CONFIG_HAS_HW_NRF_PWM1

CONFIG_HAS_HW_NRF_PWM2

CONFIG_HAS_HW_NRF_PWM3

CONFIG_HAS_HW_NRF_QDEC

CONFIG_HAS_HW_NRF_QSPI

CONFIG_HAS_HW_NRF_RADIO_BLE_CODED

CONFIG_HAS_HW_NRF_RADIO_IEEE802154

CONFIG_HAS_HW_NRF_RNG

CONFIG_HAS_HW_NRF_RTC0

CONFIG_HAS_HW_NRF_RTC1

CONFIG_HAS_HW_NRF_RTC2

CONFIG_HAS_HW_NRF_SAADC

CONFIG_HAS_HW_NRF_SPI0

CONFIG_HAS_HW_NRF_SPI1

CONFIG_HAS_HW_NRF_SPI2

CONFIG_HAS_HW_NRF_SPIM0

CONFIG_HAS_HW_NRF_SPIM1

CONFIG_HAS_HW_NRF_SPIM2

CONFIG_HAS_HW_NRF_SPIM3

CONFIG_HAS_HW_NRF_SPIS0

CONFIG_HAS_HW_NRF_SPIS1

CONFIG_HAS_HW_NRF_SPIS2

CONFIG_HAS_HW_NRF_SPIS3

CONFIG_HAS_HW_NRF_SPU

CONFIG_HAS_HW_NRF_SWI0

CONFIG_HAS_HW_NRF_SWI1

CONFIG_HAS_HW_NRF_SWI2

CONFIG_HAS_HW_NRF_SWI3

CONFIG_HAS_HW_NRF_SWI4

CONFIG_HAS_HW_NRF_SWI5

CONFIG_HAS_HW_NRF_TEMP

CONFIG_HAS_HW_NRF_TIMER0

CONFIG_HAS_HW_NRF_TIMER1

CONFIG_HAS_HW_NRF_TIMER2

CONFIG_HAS_HW_NRF_TIMER3

CONFIG_HAS_HW_NRF_TIMER4

CONFIG_HAS_HW_NRF_TWI0

CONFIG_HAS_HW_NRF_TWI1

CONFIG_HAS_HW_NRF_TWIM0

CONFIG_HAS_HW_NRF_TWIM1

CONFIG_HAS_HW_NRF_TWIM2

CONFIG_HAS_HW_NRF_TWIM3

CONFIG_HAS_HW_NRF_TWIS0

CONFIG_HAS_HW_NRF_TWIS1

CONFIG_HAS_HW_NRF_TWIS2

CONFIG_HAS_HW_NRF_TWIS3

CONFIG_HAS_HW_NRF_UART0

CONFIG_HAS_HW_NRF_UARTE0

CONFIG_HAS_HW_NRF_UARTE1

CONFIG_HAS_HW_NRF_UARTE2

CONFIG_HAS_HW_NRF_UARTE3

CONFIG_HAS_HW_NRF_USBD

CONFIG_HAS_HW_NRF_WDT

CONFIG_HAS_HW_NRF_WDT0

CONFIG_HAS_HW_NRF_WDT1

CONFIG_HAS_I2C_DW

CONFIG_HAS_IMX_CCM

Set if the CCM module is present in the SoC.

CONFIG_HAS_IMX_EPIT

Set if the EPIT module is present in the SoC.

CONFIG_HAS_IMX_GPIO

Set if the GPIO module is present in the SoC.

CONFIG_HAS_IMX_HAL

CONFIG_HAS_IMX_I2C

Set if the I2C module is present in the SoC.

CONFIG_HAS_IMX_RDC

Set if the RDC module is present in the SoC.

CONFIG_HAS_MCG

Set if the multipurpose clock generator (MCG) module is present in the SoC.

CONFIG_HAS_MCUX

CONFIG_HAS_MCUX_ADC12

Set if the 12-bit ADC (ADC12) module is present in the SoC.

CONFIG_HAS_MCUX_ADC16

Set if the 16-bit ADC (ADC16) module is present in the SoC.

CONFIG_HAS_MCUX_CACHE

Set if the L1 or L2 cache is present in the SoC.

CONFIG_HAS_MCUX_CCM

Set if the clock control module (CCM) module is present in the SoC.

CONFIG_HAS_MCUX_CSI

Set if the CMOS Sensor Interface module is present in the SoC.

CONFIG_HAS_MCUX_ELCDIF

Set if the enhanced LCD interface (eLCDIF) module is present in the SoC.

CONFIG_HAS_MCUX_ENET

Set if the ethernet (ENET) module is present in the SoC.

CONFIG_HAS_MCUX_FLEXCAN

Set if the FlexCAN module is presents in the SoC.

CONFIG_HAS_MCUX_FTFX

Set if the flash memory (FTFA, FTFE, or FTFL) module is present in the SoC.

CONFIG_HAS_MCUX_FTM

Set if the FlexTimer (FTM) module is present in the SoC.

CONFIG_HAS_MCUX_GPT

Set if the general purpose timer (GPT) module is present in the SoC.

CONFIG_HAS_MCUX_IGPIO

Set if the iMX GPIO (IGPIO) module is present in the SoC.

CONFIG_HAS_MCUX_LPI2C

Set if the low power I2C (LPI2C) module is present in the SoC.

CONFIG_HAS_MCUX_LPSCI

Set if the low power uart (LPSCI) module is present in the SoC.

CONFIG_HAS_MCUX_LPSPI

Set if the low power SPI (LPSPI) module is present in the SoC.

CONFIG_HAS_MCUX_LPUART

Set if the low power uart (LPUART) module is present in the SoC.

CONFIG_HAS_MCUX_PCC

Set if the peripheral clock controller module (PCC) module is present in the SoC.

CONFIG_HAS_MCUX_PWM

Set if the PWM module is present in the SoC.

CONFIG_HAS_MCUX_RNGA

Set if the random number generator accelerator (RNGA) module is present in the SoC.

CONFIG_HAS_MCUX_RTC

Set if the real time clock (RTC) modules is present in the SoC.

CONFIG_HAS_MCUX_SCG

Set if the system clock generator (SCG) module is present in the SoC.

CONFIG_HAS_MCUX_SIM

Set if the system integration module (SIM) module is present in the SoC.

CONFIG_HAS_MCUX_SMC

Set if the SMC module is present in the SoC.

CONFIG_HAS_MCUX_TRNG

Set if the true random number generator (TRNG) module is present in the SoC.

CONFIG_HAS_MCUX_USB_EHCI

Set if the USB controller EHCI module is present in the SoC.

CONFIG_HAS_MCUX_USDHC1

Set if the USDHC instance 1 module is present in the SoC.

CONFIG_HAS_MCUX_USDHC2

Set if the USDHC2 instance 2 module is present in the SoC.

CONFIG_HAS_MCUX_WDOG32

Set if the watchdog (WDOG32) module is present in the SoC.

CONFIG_HAS_MEC_HAL

Microchip MEC HAL drivers support

CONFIG_HAS_MSP432P4XXSDK

CONFIG_HAS_MULX_INSTRUCTION

CONFIG_HAS_MUL_INSTRUCTION

CONFIG_HAS_NORDIC_DRIVERS

CONFIG_HAS_NRFX

CONFIG_HAS_OSC

Set if the oscillator (OSC) module is present in the SoC.

CONFIG_HAS_RV32M1_FTFX

Set if the flash memory (FTFA, FTFE, or FTFL) module is present in the SoC.

CONFIG_HAS_RV32M1_LPI2C

Set if the low power i2c (LPI2C) module is present in the SoC.

CONFIG_HAS_RV32M1_LPSPI

Set if the low power spi (LPSPI) module is present in the SoC.

CONFIG_HAS_RV32M1_LPUART

Set if the low power uart (LPUART) module is present in the SoC.

CONFIG_HAS_SDL

This option specifies that the target board has SDL support

CONFIG_HAS_SEGGER_RTT

CONFIG_HAS_SILABS_GECKO

CONFIG_HAS_SPI_DW

Signifies whether DesignWare SPI compatible HW is available

CONFIG_HAS_STLIB

CONFIG_HAS_STM32CUBE

CONFIG_HAS_STMEMSC

CONFIG_HAS_SWO

When enabled, indicates that SoC has an SWO output

CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1

This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1 configuration option.

CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_2

This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2 configuration option.

CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_3

This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3 configuration option.

CONFIG_HAS_SYS_POWER_STATE_SLEEP_1

This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1 configuration option.

CONFIG_HAS_SYS_POWER_STATE_SLEEP_2

This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2 configuration option.

CONFIG_HAS_SYS_POWER_STATE_SLEEP_3

This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3 configuration option.

CONFIG_HAS_WDT_MULTISTAGE

CONFIG_HAVE_CUSTOM_LINKER_SCRIPT

Set this option if you have a custom linker script which needed to be define in CUSTOM_LINKER_SCRIPT.

CONFIG_HEAP_MEM_POOL_MIN_SIZE

This option specifies the size of the smallest block in the pool. Option must be a power of 2 and lower than or equal to the size of the entire pool.

CONFIG_HEAP_MEM_POOL_SIZE

This option specifies the size of the heap memory pool used when dynamically allocating memory using k_malloc(). Supported values are: 256, 1024, 4096, and 16384. A size of zero means that no heap memory pool is defined.

CONFIG_HID_INTERRUPT_EP_MPS

USB HID Device interrupt endpoint size

CONFIG_HMC5883L

Enable driver for HMC5883L I2C-based magnetometer.

CONFIG_HMC5883L_FS

Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 0.88, 1.3, 1.9, 2.5, 4, 4.7, 5.6 and 8.1.

CONFIG_HMC5883L_ODR

Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.75, 1.5, 3, 7.5, 15, 30 and 75.

CONFIG_HMC5883L_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_HMC5883L_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_HMC5883L_TRIGGER

CONFIG_HMC5883L_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_HMC5883L_TRIGGER_NONE

No trigger

CONFIG_HMC5883L_TRIGGER_OWN_THREAD

Use own thread

CONFIG_HP206C

Enable HopeRF HP206C barometer and altimeter support.

CONFIG_HP206C_ALT_OFFSET

Value, in cm, that will be used to compensate altitude calculation. For more info on how to choose this value, consult section 6.1.1 in the datasheet.

CONFIG_HP206C_ALT_OFFSET_RUNTIME

Altitude offset set at runtime

CONFIG_HP206C_OSR

Allowed values: 4096, 2048, 1024, 512, 256, 128

CONFIG_HP206C_OSR_RUNTIME

Oversampling rate set at runtime

CONFIG_HPET_TIMER

This option selects High Precision Event Timer (HPET) as a system timer.

CONFIG_HT16K33

Enable LED driver for HT16K33.

The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports up to 128 LEDs (up to 16 rows and 8 commons).

CONFIG_HT16K33_KEYSCAN

Enable keyscan child device support in the HT16K33 LED driver.

The keyscan functionality itself is handled by the HT16K33 GPIO driver.

CONFIG_HT16K33_KEYSCAN_DEBOUNCE_MSEC

Keyscan debounce interval in milliseconds.

CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_PRIO

Priority level for internal thread for keyscan interrupt processing.

CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_STACK_SIZE

Size of the stack used for internal thread for keyscan interrupt processing.

CONFIG_HT16K33_KEYSCAN_POLL_MSEC

Keyscan poll interval in milliseconds. Polling is only used if no interrupt line is present.

CONFIG_HTS221

Enable driver for HTS221 I2C-based temperature and humidity sensor.

CONFIG_HTS221_ODR

Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7 and 12.5.

CONFIG_HTS221_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_HTS221_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_HTS221_TRIGGER

CONFIG_HTS221_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_HTS221_TRIGGER_NONE

No trigger

CONFIG_HTS221_TRIGGER_OWN_THREAD

Use own thread

CONFIG_HTTP_CLIENT

HTTP client API

CONFIG_HTTP_PARSER

This option enables the http_parser library from nodejs. This parser requires some string-related routines commonly provided by a libc implementation.

CONFIG_HTTP_PARSER_STRICT

This option enables the strict parsing option

CONFIG_HTTP_PARSER_URL

This option enables the URI parser library based on source from nodejs. This parser requires some string-related routines commonly provided by a libc implementation.

CONFIG_HWINFO

Enable hwinfo driver.

CONFIG_HWINFO_ESP32

Enable ESP32 hwinfo driver.

CONFIG_HWINFO_IMXRT

Enable NXP i.mx RT hwinfo driver.

CONFIG_HWINFO_LITEX

Enable LiteX hwinfo driver

CONFIG_HWINFO_MCUX_SIM

Enable NXP kinetis mcux hwinfo driver.

CONFIG_HWINFO_NRF

Enable Nordic NRF hwinfo driver.

CONFIG_HWINFO_SAM

Enable Atmel SAM hwinfo driver.

CONFIG_HWINFO_SAM0

Enable Atmel SAM0 hwinfo driver.

CONFIG_HWINFO_SHELL

Enable hwinfo Shell for testing.

CONFIG_HWINFO_STM32

Enable STM32 hwinfo driver.

CONFIG_HW_STACK_PROTECTION

Select this option to enable hardware-based platform features to catch stack overflows when the system is running in privileged mode. If CONFIG_USERSPACE is not enabled, the system is always running in privileged mode.

Note that this does not necessarily prevent corruption and assertions about the overall system state when a fault is triggered cannot be made.

CONFIG_I2C

Enable I2C Driver Configuration

CONFIG_I2C_0

Enable I2C Port 0

CONFIG_I2C_0_IRQ_PRI

IRQ priority.

CONFIG_I2C_0_NRF_TWI

Enable nRF TWI Master without EasyDMA on port 0.

CONFIG_I2C_0_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 0. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_1

Enable I2C Port 1

CONFIG_I2C_1_NRF_TWI

Enable nRF TWI Master without EasyDMA on port 1.

CONFIG_I2C_1_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 1. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_2

Enable I2C Port 2

CONFIG_I2C_2_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 2. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_3

Enable I2C Port 3

CONFIG_I2C_3_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 3. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_4

Enable I2C Port 4

CONFIG_I2C_5

Enable I2C Port 5

CONFIG_I2C_6

Enable I2C Port 6

CONFIG_I2C_7

Enable I2C Port 7

CONFIG_I2C_BITBANG

Enable library used for software driven (bit banging) I2C support

CONFIG_I2C_CC13XX_CC26XX

Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series.

CONFIG_I2C_CC32XX

Enable the CC32XX I2C driver.

CONFIG_I2C_DW

Enable the Design Ware I2C driver

CONFIG_I2C_DW_CLOCK_SPEED

Set the clock speed for I2C

CONFIG_I2C_EEPROM_SLAVE

Enable virtual I2C Slave EEPROM driver

CONFIG_I2C_ESP32

Enables the ESP32 I2C driver

CONFIG_I2C_ESP32_0_IRQ

Port 0 IRQ line

CONFIG_I2C_ESP32_0_RX_LSB_FIRST

Port 0 Receive LSB first

CONFIG_I2C_ESP32_0_TX_LSB_FIRST

Port 0 Transmit LSB first

CONFIG_I2C_ESP32_1_IRQ

Port 1 IRQ line

CONFIG_I2C_ESP32_1_RX_LSB_FIRST

Port 1 Receive LSB first

CONFIG_I2C_ESP32_1_TX_LSB_FIRST

Port 1 Transmit LSB first

CONFIG_I2C_ESP32_TIMEOUT

I2C timeout to receive a data bit in APB clock cycles

CONFIG_I2C_GECKO

Enable the SiLabs Gecko I2C bus driver.

CONFIG_I2C_GPIO

Enable software driven (bit banging) I2C support using GPIO pins

CONFIG_I2C_GPIO_0

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_0_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_0_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_0_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_0_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_1

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_1_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_1_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_1_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_1_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_2

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_2_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_2_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_2_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_2_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_3

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_3_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_3_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_3_SCL_PIN

This is the GPIO pin number for the I2C SCL line

CONFIG_I2C_GPIO_3_SDA_PIN

This is the GPIO pin number for the I2C SDA line

CONFIG_I2C_IMX

Enable the i.MX I2C driver.

CONFIG_I2C_INIT_PRIORITY

I2C device driver initialization priority.

CONFIG_I2C_LOG_LEVEL

CONFIG_I2C_LOG_LEVEL_DBG

Debug

CONFIG_I2C_LOG_LEVEL_ERR

Error

CONFIG_I2C_LOG_LEVEL_INF

Info

CONFIG_I2C_LOG_LEVEL_OFF

Off

CONFIG_I2C_LOG_LEVEL_WRN

Warning

CONFIG_I2C_MCUX

Enable the mcux I2C driver.

CONFIG_I2C_MCUX_LPI2C

Enable the mcux LPI2C driver.

CONFIG_I2C_NIOS2

Enable the Nios-II I2C driver.

CONFIG_I2C_NRFX

Enable support for nrfx TWI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. I2C_0 and SPI_0. You may need to disable SPI_0 or SPI_1.

CONFIG_I2C_RV32M1_LPI2C

Enable the RV32M1 LPI2C driver.

CONFIG_I2C_SAM0

Enable the SAM0 series SERCOM I2C driver.

CONFIG_I2C_SAM0_DMA_DRIVEN

This enables DMA driven transactions for the I2C peripheral. DMA driven mode requires fewer interrupts to handle the transaction and ensures that high speed modes are not delayed by data reloading.

CONFIG_I2C_SAM_TWI

Enable Atmel SAM MCU Family (TWI) I2C bus driver.

CONFIG_I2C_SAM_TWIHS

Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.

CONFIG_I2C_SBCON

I2C driver for ARM’s SBCon two-wire serial bus interface

CONFIG_I2C_SIFIVE

Enable I2C support on SiFive Freedom

CONFIG_I2C_SLAVE

Enable I2C Slave Driver Configuration

CONFIG_I2C_SLAVE_INIT_PRIORITY

I2C Slave device driver initialization priority.

CONFIG_I2C_STM32

Enable I2C support on the STM32 SoCs

CONFIG_I2C_STM32_COMBINED_INTERRUPT

CONFIG_I2C_STM32_INTERRUPT

Enable Interrupt support for the I2C Driver

CONFIG_I2C_STM32_V1

Enable I2C support on the STM32 F1 and F4X family of processors. This driver also supports the F2 and L1 series.

CONFIG_I2C_STM32_V2

Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1 and G4 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode is only supported by this driver with interrupts enabled.

CONFIG_I2C_XEC

Enable the Microchip XEC I2C driver.

CONFIG_I2C_XEC_0

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_XEC_1

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_XEC_2

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2S

Enable support for the I2S (Inter-IC Sound) hardware bus.

CONFIG_I2S_1

Enable I2S controller port 1.

CONFIG_I2S_2

Enable I2S controller port 2.

CONFIG_I2S_3

Enable I2S controller port 3.

CONFIG_I2S_4

Enable I2S controller port 4.

CONFIG_I2S_5

Enable I2S controller port 5.

CONFIG_I2S_CAVS

Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module.

CONFIG_I2S_CAVS_1_DMA_RX_CHANNEL

DMA channel number to use for I2S1 RX transfer.

CONFIG_I2S_CAVS_1_DMA_TX_CHANNEL

DMA channel number to use for I2S1 TX transfer.

CONFIG_I2S_CAVS_1_NAME

I2S 1 device name

CONFIG_I2S_CAVS_2_DMA_RX_CHANNEL

DMA channel number to use for I2S2 RX transfer.

CONFIG_I2S_CAVS_2_DMA_TX_CHANNEL

DMA channel number to use for I2S2 TX transfer.

CONFIG_I2S_CAVS_2_NAME

I2S 2 device name

CONFIG_I2S_CAVS_3_DMA_RX_CHANNEL

DMA channel number to use for I2S3 RX transfer.

CONFIG_I2S_CAVS_3_DMA_TX_CHANNEL

DMA channel number to use for I2S3 TX transfer.

CONFIG_I2S_CAVS_3_NAME

I2S 3 device name

CONFIG_I2S_CAVS_DMA_NAME

Name of the DMA device this device driver can use.

CONFIG_I2S_CAVS_IRQ_PRI

Interrupt priority

CONFIG_I2S_INIT_PRIORITY

Device driver initialization priority.

CONFIG_I2S_LOG_LEVEL

CONFIG_I2S_LOG_LEVEL_DBG

Debug

CONFIG_I2S_LOG_LEVEL_ERR

Error

CONFIG_I2S_LOG_LEVEL_INF

Info

CONFIG_I2S_LOG_LEVEL_OFF

Off

CONFIG_I2S_LOG_LEVEL_WRN

Warning

CONFIG_I2S_SAM_SSC

Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module.

CONFIG_I2S_SAM_SSC_0_DMA_RX_CHANNEL

DMA channel number to use for RX transfers.

CONFIG_I2S_SAM_SSC_0_DMA_TX_CHANNEL

DMA channel number to use for TX transfers.

CONFIG_I2S_SAM_SSC_0_IRQ_PRI

Interrupt priority

CONFIG_I2S_SAM_SSC_0_NAME

I2S 0 device name

CONFIG_I2S_SAM_SSC_0_PIN_RF_EN

If enabled RF signal is connected to RF pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode.

If disabled RF signal is disconnected from RF pin and connected internally to TF (Transmitter Frame Synchro signal).

CONFIG_I2S_SAM_SSC_0_PIN_RK_EN

If enabled RK signal is connected to RK pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode.

If disabled RK signal is disconnected from RK pin and connected internally to TK (Transmitter Clock signal).

CONFIG_I2S_SAM_SSC_0_PIN_TD_PB5

PB5

CONFIG_I2S_SAM_SSC_0_PIN_TD_PD10

PD10

CONFIG_I2S_SAM_SSC_0_PIN_TD_PD26

PD26

CONFIG_I2S_SAM_SSC_DMA_NAME

Name of the DMA device this device driver can use.

CONFIG_I2S_SAM_SSC_RX_BLOCK_COUNT

RX queue length

CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT

TX queue length

CONFIG_I2S_STM32

Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series)

CONFIG_I2S_STM32_PLLI2S_PLLM

Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

CONFIG_I2S_STM32_PLLI2S_PLLN

Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432

CONFIG_I2S_STM32_PLLI2S_PLLR

Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7

CONFIG_I2S_STM32_RX_BLOCK_COUNT

RX queue length

CONFIG_I2S_STM32_TX_BLOCK_COUNT

TX queue length

CONFIG_I2S_STM32_USE_PLLI2S_ENABLE

Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE.

CONFIG_IAQ_CORE_MAX_READ_RETRIES

Number of retries when reading failed or device not ready.

CONFIG_IDLE_STACK_SIZE

Depending on the work that the idle task must do, most likely due to power management but possibly to other features like system event logging (e.g. logging when the system goes to sleep), the idle thread may need more stack space than the default value.

CONFIG_IDT_NUM_VECTORS

This option specifies the number of interrupt vector entries in the Interrupt Descriptor Table (IDT). By default all 256 vectors are supported in an IDT requiring 2048 bytes of memory.

CONFIG_IEEE802154

IEEE 802.15.4 drivers options

CONFIG_IEEE802154_CC1200

TI CC1200 Driver support

CONFIG_IEEE802154_CC1200_CCA_THRESHOLD

Set the CCA threshold. See datasheet’s AGC_CS_THR register for more information. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC1200_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_CC1200_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_IEEE802154_CC1200_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc1200 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_CC1200_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_CC1200_PKTCFG0

CONFIG_IEEE802154_CC1200_PKTCFG1

CONFIG_IEEE802154_CC1200_PKTCFG2

CONFIG_IEEE802154_CC1200_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IEEE802154_CC1200_RFEND_CFG0

CONFIG_IEEE802154_CC1200_RFEND_CFG1

CONFIG_IEEE802154_CC1200_RF_PRESET

Use TI CC1200 RF pre-sets

CONFIG_IEEE802154_CC1200_RF_SET_0

868MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI

CONFIG_IEEE802154_CC1200_RF_SET_1

920MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ARIB

CONFIG_IEEE802154_CC1200_RF_SET_2

434MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI

CONFIG_IEEE802154_CC1200_RSSI_OFFSET

Set the gain adjustment. See datasheet’s AGC_GAIN_ADJUST register for more information. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC1200_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_CC1200_SETTLING_CFG

CONFIG_IEEE802154_CC1200_XOSC

This sets the XOSC value, it must be between 38400 and 40000. This value should follow what has been set in the RF settings via SmartRF tool. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC13XX_CC26XX

TI CC13xx / CC26xx IEEE 802.15.4 driver support

CONFIG_IEEE802154_CC13XX_CC26XX_DRV_NAME

This option sets the driver name.

CONFIG_IEEE802154_CC13XX_CC26XX_INIT_PRIO

Set the initialization priority number.

CONFIG_IEEE802154_CC13XX_CC26XX_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread.

CONFIG_IEEE802154_CC2520

TI CC2520 Driver support

CONFIG_IEEE802154_CC2520_CRYPTO

This option will expose the hardware AES encryption from CC2520. Such feature should not be used for anything but 802.15.4 security. The crypto device exposed will only support synchronous CCM operation.

CONFIG_IEEE802154_CC2520_CRYPTO_DRV_NAME

This option sets the driver name for the crypto part found on CC2520.

CONFIG_IEEE802154_CC2520_CRYPTO_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. It should be initialized after CC2520 as it shares the same runtime context.

CONFIG_IEEE802154_CC2520_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_CC2520_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_IEEE802154_CC2520_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc2520 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_CC2520_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_CC2520_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IEEE802154_CC2520_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_DRIVER_LOG_LEVEL

CONFIG_IEEE802154_DRIVER_LOG_LEVEL_DBG

Debug

CONFIG_IEEE802154_DRIVER_LOG_LEVEL_ERR

Error

CONFIG_IEEE802154_DRIVER_LOG_LEVEL_INF

Info

CONFIG_IEEE802154_DRIVER_LOG_LEVEL_OFF

Off

CONFIG_IEEE802154_DRIVER_LOG_LEVEL_WRN

Warning

CONFIG_IEEE802154_KW41Z

NXP KW41Z Driver support

CONFIG_IEEE802154_KW41Z_DRV_NAME

This option sets the driver name. Do not change it unless you know what you are doing.

CONFIG_IEEE802154_KW41Z_INIT_PRIO

Set the initialization priority number. Do not change it unless you know what you are doing. It has to start before the net stack.

CONFIG_IEEE802154_MCR20A

NXP MCR20A Driver support

CONFIG_IEEE802154_MCR20A_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_MCR20A_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware mcr20a requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_NRF5

nRF52 series IEEE 802.15.4 Driver

CONFIG_IEEE802154_NRF5_CCA_CORR_LIMIT

Limit for occurrences above correlator threshold. When not equal to zero the correlator based signal detect is enabled.

CONFIG_IEEE802154_NRF5_CCA_CORR_THRESHOLD

nRF52 IEEE 802.15.4 CCA Correlator threshold

CONFIG_IEEE802154_NRF5_CCA_ED_THRESHOLD

If energy detected in a given channel is above the value then the channel is deemed busy. The unit is defined as per 802.15.4-2006 spec.

CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER

Carrier Seen

CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER_AND_ED

Energy Above Threshold AND Carrier Seen

CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER_OR_ED

Energy Above Threshold OR Carrier Seen

CONFIG_IEEE802154_NRF5_CCA_MODE_ED

Energy Above Threshold

CONFIG_IEEE802154_NRF5_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_NRF5_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing.

CONFIG_IEEE802154_NRF5_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_RAW_MODE

This option enables using the drivers in a so-called “raw” mode, i.e. without a MAC stack (the net L2 layer for 802.15.4 will not be built). Used only for very specific cases, such as wpan_serial and wpanusb samples.

CONFIG_IEEE802154_UPIPE

UART PIPE fake radio driver support for QEMU

CONFIG_IEEE802154_UPIPE_DRV_NAME

UART PIPE Driver name

CONFIG_IEEE802154_UPIPE_HW_FILTER

This option assure the driver will process just frames addressed to him.

CONFIG_IEEE802154_UPIPE_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_UPIPE_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IIS3DHHC

Enable driver for IIS3DHHC SPI-based accelerometer sensor.

CONFIG_IIS3DHHC_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_IIS3DHHC_NORM_MODE

Enable Sensor at 1KHz

CONFIG_IIS3DHHC_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_IIS3DHHC_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_IIS3DHHC_TRIGGER

CONFIG_IIS3DHHC_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_IIS3DHHC_TRIGGER_NONE

No trigger

CONFIG_IIS3DHHC_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ILI9340

Enable driver for ILI9340 display driver.

CONFIG_ILI9340_LCD_ADAFRUIT_1480

Adafruit 2.2” TFT 1480

CONFIG_ILI9340_LCD_SEEED_TFTV2

Seeed 2.8” TFT v2.0

CONFIG_ILI9340_RGB565

RGB565

CONFIG_ILI9340_RGB888

RGB888

CONFIG_IMAGE_VECTOR_TABLE_OFFSET

The Image Vector Table (IVT) provides the boot ROM with pointers to the application entry point and device configuration data. The boot ROM requires a fixed IVT offset for each type of boot device.

CONFIG_IMG_BLOCK_BUF_SIZE

Size (in Bytes) of buffer for image writer. Must be a multiple of the access alignment required by used flash driver.

CONFIG_IMG_ERASE_PROGRESSIVELY

If enabled, flash is erased as necessary when receiving new firmware, instead of erasing the whole image slot at once. This is necessary on some hardware that has long erase times, to prevent long wait times at the beginning of the DFU process.

CONFIG_IMG_MANAGER

Enable support for managing DFU image.

CONFIG_IMG_MANAGER_LOG_LEVEL

CONFIG_IMG_MANAGER_LOG_LEVEL_DBG

Debug

CONFIG_IMG_MANAGER_LOG_LEVEL_ERR

Error

CONFIG_IMG_MANAGER_LOG_LEVEL_INF

Info

CONFIG_IMG_MANAGER_LOG_LEVEL_OFF

Off

CONFIG_IMG_MANAGER_LOG_LEVEL_WRN

Warning

CONFIG_IMG_MGMT_UL_CHUNK_SIZE

Limits the maximum chunk size for image uploads, in bytes. A buffer of this size gets allocated on the stack during handling of a image upload command.

CONFIG_INCLUDE_RESET_VECTOR

Include the reset vector stub, which enables instruction/data caches and then jumps to __start. This code is typically located at the very beginning of flash memory. You may need to omit this if using the nios2-download tool since it refuses to load data anywhere other than RAM.

CONFIG_INIT_ARM_PLL

Initialize ARM PLL

CONFIG_INIT_ENET_PLL

If y, the Ethernet PLL is initialized. Always enabled on e.g. MIMXRT1021 - see commit 17f4d6bec7 (“soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021”).

CONFIG_INIT_STACKS

This option instructs the kernel to initialize stack areas with a known value (0xaa) before they are first used, so that the high water mark can be easily determined. This applies to the stack areas for threads, as well as to the interrupt stack.

CONFIG_INIT_SYS_PLL

Initialize SYS PLL

CONFIG_INIT_USB1_PLL

Initialize USB1 PLL

CONFIG_INIT_VIDEO_PLL

Initialize Video PLL

CONFIG_INTEL_GNA

Enable support for Intel’s GMM and Neural Network Accelerator

CONFIG_INTEL_GNA_INIT_PRIORITY

Device driver initialization priority.

CONFIG_INTEL_GNA_MAX_MODELS

Max. number of unique neural network models required in the system

CONFIG_INTEL_GNA_MAX_PENDING_REQUESTS

Maximum number of pending inference requests in the driver

CONFIG_INTEL_GNA_NAME

Name of the GNA device this device driver can use.

CONFIG_INTEL_GNA_POWER_MODE

Sets GNA operation mode for power saving Levels are: 0 ALWAYS_ON, GNA is always on with very minimal power save 1 CLOCK_GATED, GNA clock is gated when not active 2 POWER_GATED, GNA clock and power are gated when not active 3 ALWAYS_OFF, GNA is tuned off and never used in the system

CONFIG_IOAPIC

This option signifies that the target has an IO-APIC device. This capability allows IO-APIC-dependent code to be included.

CONFIG_IOAPIC_MASK_RTE

At boot, mask all IOAPIC RTEs if they may be in an undefined state. You don’t need this if the RTEs are either all guaranteed to be masked when the OS starts up, or a previous boot stage has done some IOAPIC configuration that needs to be preserved.

CONFIG_IOAPIC_NUM_RTES

This option indicates the maximum number of Redirection Table Entries (RTEs) (one per IRQ available to the IO-APIC) made available to the kernel, regardless of the number provided by the hardware itself. For most efficient usage of memory, it should match the number of IRQ lines needed by devices connected to the IO-APIC.

CONFIG_IPG_DIV

IPG clock divider

CONFIG_IPM

Include interrupt-based inter-processor mailboxes drivers in system configuration

CONFIG_IPM_CONSOLE_RECEIVER

Enable the receiving side of IPM console

CONFIG_IPM_CONSOLE_SENDER

Enable the sending side of IPM console

CONFIG_IPM_CONSOLE_STACK_SIZE

Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here.

CONFIG_IPM_IMX

Driver for NXP i.MX messaging unit

CONFIG_IPM_IMX_MAX_DATA_SIZE

CONFIG_IPM_IMX_MAX_DATA_SIZE_16

There will be a single message type with id 0 and a maximum size of 16 bytes.

CONFIG_IPM_IMX_MAX_DATA_SIZE_4

There will be four message types with ids 0, 1, 2 or 3 and a maximum size of 4 bytes each.

CONFIG_IPM_IMX_MAX_DATA_SIZE_8

There will be two message types with ids 0 or 1 and a maximum size of 8 bytes each.

CONFIG_IPM_IMX_MAX_ID_VAL

CONFIG_IPM_LOG_LEVEL

CONFIG_IPM_LOG_LEVEL_DBG

Debug

CONFIG_IPM_LOG_LEVEL_ERR

Error

CONFIG_IPM_LOG_LEVEL_INF

Info

CONFIG_IPM_LOG_LEVEL_OFF

Off

CONFIG_IPM_LOG_LEVEL_WRN

Warning

CONFIG_IPM_MCUX

Driver for MCUX mailbox

CONFIG_IPM_MHU

Driver for SSE 200 MHU (Message Handling Unit)

CONFIG_IPM_MSG_CH_0_ENABLE

Enable IPM Message Channel 0

CONFIG_IPM_MSG_CH_0_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_0_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_10_ENABLE

Enable IPM Message Channel 10

CONFIG_IPM_MSG_CH_10_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_10_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_11_ENABLE

Enable IPM Message Channel 11

CONFIG_IPM_MSG_CH_11_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_11_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_12_ENABLE

Enable IPM Message Channel 12

CONFIG_IPM_MSG_CH_12_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_12_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_13_ENABLE

Enable IPM Message Channel 13

CONFIG_IPM_MSG_CH_13_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_13_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_14_ENABLE

Enable IPM Message Channel 14

CONFIG_IPM_MSG_CH_14_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_14_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_15_ENABLE

Enable IPM Message Channel 15

CONFIG_IPM_MSG_CH_15_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_15_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_1_ENABLE

Enable IPM Message Channel 1

CONFIG_IPM_MSG_CH_1_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_1_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_2_ENABLE

Enable IPM Message Channel 2

CONFIG_IPM_MSG_CH_2_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_2_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_3_ENABLE

Enable IPM Message Channel 3

CONFIG_IPM_MSG_CH_3_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_3_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_4_ENABLE

Enable IPM Message Channel 4

CONFIG_IPM_MSG_CH_4_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_4_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_5_ENABLE

Enable IPM Message Channel 5

CONFIG_IPM_MSG_CH_5_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_5_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_6_ENABLE

Enable IPM Message Channel 6

CONFIG_IPM_MSG_CH_6_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_6_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_7_ENABLE

Enable IPM Message Channel 7

CONFIG_IPM_MSG_CH_7_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_7_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_8_ENABLE

Enable IPM Message Channel 8

CONFIG_IPM_MSG_CH_8_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_8_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_9_ENABLE

Enable IPM Message Channel 9

CONFIG_IPM_MSG_CH_9_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_9_TX

IPM Message TX Channel

CONFIG_IPM_NRFX

Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW.

CONFIG_IPM_NRF_SINGLE_INSTANCE

Enable this option if the IPM device should have a single instance, instead of one per IPC message channel.

CONFIG_IPM_STM32_IPCC

Driver for stm32 IPCC mailboxes

CONFIG_IPM_STM32_IPCC_PROCID

use to define the Processor ID for IPCC access

CONFIG_IRQ_OFFLOAD

Enable irq_offload() API which allows functions to be synchronously run in interrupt context. Only useful for test cases that need to validate the correctness of kernel objects in IRQ context.

CONFIG_IRQ_OFFLOAD_INTNUM

The index of the software interrupt to be used for IRQ offload.

Please note that in order for IRQ offload to work correctly the selected interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.

CONFIG_IRQ_OFFLOAD_VECTOR

IDT vector to use for IRQ offload

CONFIG_ISA_ARM

From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets

A32 instructions, known as Arm instructions in pre-Armv8 architectures, are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions are supported by both A-profile and R-profile architectures.

A32 was traditionally used in applications requiring the highest performance, or for handling hardware exceptions such as interrupts and processor start-up. Much of its functionality was subsumed into T32 with the introduction of Thumb-2 technology.

CONFIG_ISA_THUMB2

From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php

Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications.

Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems.

The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb.

For performance optimized code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the processor, and in all ARMv7 architecture-based processors.

CONFIG_ISL29035

Enable driver for the ISL29035 light sensor.

CONFIG_ISL29035_INTEGRATION_TIME_105K

105 ms

CONFIG_ISL29035_INTEGRATION_TIME_26

0.0256 ms

CONFIG_ISL29035_INTEGRATION_TIME_410

0.41 ms

CONFIG_ISL29035_INTEGRATION_TIME_6500

6.5 ms

CONFIG_ISL29035_INT_PERSIST_1

1

CONFIG_ISL29035_INT_PERSIST_16

16

CONFIG_ISL29035_INT_PERSIST_4

4

CONFIG_ISL29035_INT_PERSIST_8

8

CONFIG_ISL29035_LUX_RANGE_16K

16000

CONFIG_ISL29035_LUX_RANGE_1K

1000

CONFIG_ISL29035_LUX_RANGE_4K

4000

CONFIG_ISL29035_LUX_RANGE_64K

64000

CONFIG_ISL29035_MODE_ALS

Sensing mode for ambient light spectrum.

CONFIG_ISL29035_MODE_IR

Sensing mode for infrared spectrum.

CONFIG_ISL29035_THREAD_PRIORITY

Priority of thread used to handle the timer and threshold triggers.

CONFIG_ISL29035_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ISL29035_TRIGGER

CONFIG_ISL29035_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ISL29035_TRIGGER_NONE

No trigger

CONFIG_ISL29035_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ISR_DEPTH

The more nesting allowed, the more room is required for IRQ stacks.

CONFIG_ISR_STACK_SIZE

This option specifies the size of the stack used by interrupt service routines (ISRs), and during kernel initialization.

CONFIG_ISR_SUBSTACK_SIZE

Number of bytes from the ISR stack to reserve for each nested IRQ level. Must be a multiple of 16 to main stack alignment. Note that CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH must be equal to CONFIG_ISR_STACK_SIZE.

CONFIG_IS_BOOTLOADER

This option indicates that Zephyr will act as a bootloader to execute a separate Zephyr image payload.

CONFIG_IWDG_STM32

Enable IWDG driver for STM32 line of MCUs

CONFIG_IWDG_STM32_START_AT_BOOT

Enable this setting to allow IWDG to be automatically started during device initialization. Note that once IWDG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset.

CONFIG_IWDG_STM32_TIMEOUT

Set timeout value for IWDG in microseconds. The min timeout supported is 0.1ms, the max timeout is 26214.4ms.

CONFIG_JSON_LIBRARY

Build a minimal JSON parsing/encoding library. Used by sample applications such as the NATS client.

CONFIG_JWT

Enable creation of JWT tokens

CONFIG_JWT_SIGN_ECDSA

Use ECDSA signature (ES-256)

CONFIG_JWT_SIGN_RSA

Use RSA signature (RS-256)

CONFIG_K22_BUS_CLOCK_DIVIDER

This option specifies the divide value for the K22 bus clock from the system clock.

CONFIG_K22_CORE_CLOCK_DIVIDER

This option specifies the divide value for the K22 processor core clock from the system clock.

CONFIG_K22_FLASH_CLOCK_DIVIDER

This option specifies the divide value for the K64 flash clock from the system clock.

CONFIG_K22_FLEXBUS_CLOCK_DIVIDER

This option specifies the divide value for the K22 FlexBus clock from the system clock.

CONFIG_K64_BUS_CLOCK_DIVIDER

This option specifies the divide value for the K64 bus clock from the system clock.

CONFIG_K64_CORE_CLOCK_DIVIDER

This option specifies the divide value for the K64 processor core clock from the system clock.

CONFIG_K64_FLASH_CLOCK_DIVIDER

This option specifies the divide value for the K64 flash clock from the system clock.

CONFIG_K64_FLEXBUS_CLOCK_DIVIDER

This option specifies the divide value for the K64 FlexBus clock from the system clock.

CONFIG_K8X_BUS_CLOCK_DIVIDER

This option specifies the divide value for the K8x bus clock from the system clock.

CONFIG_K8X_CORE_CLOCK_DIVIDER

This option specifies the divide value for the K8x processor core clock from the system clock.

CONFIG_K8X_FLASH_CLOCK_DIVIDER

This option specifies the divide value for the K8x flash clock from the system clock.

CONFIG_K8X_FLEXBUS_CLOCK_DIVIDER

This option specifies the divide value for the K8x FlexBus clock from the system clock.

CONFIG_KERNEL_BIN_NAME

This option sets the name of the generated kernel binary.

CONFIG_KERNEL_DEBUG

Enable kernel debugging.

Note that debugging the kernel internals can be very verbose.

CONFIG_KERNEL_ENTRY

Code entry symbol, to be set at linking phase.

CONFIG_KERNEL_INIT_PRIORITY_DEFAULT

Default minimal init priority for each init level.

CONFIG_KERNEL_INIT_PRIORITY_DEVICE

Device driver, that depends on common components, such as interrupt controller, but does not depend on other devices, uses this init priority.

CONFIG_KERNEL_INIT_PRIORITY_OBJECTS

Kernel objects use this priority for initialization. This priority needs to be higher than minimal default initialization priority.

CONFIG_KERNEL_LOG_LEVEL

CONFIG_KERNEL_LOG_LEVEL_DBG

Debug

CONFIG_KERNEL_LOG_LEVEL_ERR

Error

CONFIG_KERNEL_LOG_LEVEL_INF

Info

CONFIG_KERNEL_LOG_LEVEL_OFF

Off

CONFIG_KERNEL_LOG_LEVEL_WRN

Warning

CONFIG_KERNEL_SHELL

This shell provides access to basic kernel data like version, uptime and other useful information.

CONFIG_KINETIS_FLASH_CONFIG

Include the 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFx module.

CONFIG_KINETIS_FLASH_CONFIG_FDPROT

Configures the reset value of the FDPROT register for FlexNVM devices. For program flash only devices, this byte is reserved.

CONFIG_KINETIS_FLASH_CONFIG_FEPROT

Configures the reset value of the FEPROT register for FlexNVM devices. For program flash only devices, this byte is reserved.

CONFIG_KINETIS_FLASH_CONFIG_FOPT

Configures the reset value of the FOPT register, which includes boot, NMI, and EzPort options.

CONFIG_KINETIS_FLASH_CONFIG_FSEC

Configures the reset value of the FSEC register, which includes backdoor key access, mass erase, factory access, and flash security options.

CONFIG_KINETIS_FLASH_CONFIG_OFFSET

Kinetis flash configuration field offset

CONFIG_KINETIS_KE1XF_ENABLE_CODE_CACHE

Enable the code cache

CONFIG_KOBJECT_TEXT_AREA

Size of kernel object text area. Used in linker script.

CONFIG_KSCAN

Include Keyboard scan drivers in system config.

CONFIG_KSCAN_INIT_PRIORITY

Keyboard scan device driver initialization priority.

CONFIG_KSCAN_LOG_LEVEL

CONFIG_KSCAN_LOG_LEVEL_DBG

Debug

CONFIG_KSCAN_LOG_LEVEL_ERR

Error

CONFIG_KSCAN_LOG_LEVEL_INF

Info

CONFIG_KSCAN_LOG_LEVEL_OFF

Off

CONFIG_KSCAN_LOG_LEVEL_WRN

Warning

CONFIG_KSCAN_XEC

Enable the Microchip XEC Kscan IO driver.

CONFIG_KSCAN_XEC_COLUMN_SIZE

Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17).

CONFIG_KSCAN_XEC_DEBOUNCE_DOWN

Determines the time in msecs for debouncing a key press.

CONFIG_KSCAN_XEC_DEBOUNCE_UP

Determines the time in msecs for debouncing a key release.

CONFIG_KSCAN_XEC_POLL_PERIOD

Defines the poll period in msecs between between matrix scans.

CONFIG_KSCAN_XEC_ROW_SIZE

Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7).

CONFIG_KV5X_BUS_CLOCK_DIVIDER

This option specifies the divide value for the KV5X bus clock from the system clock.

CONFIG_KV5X_CORE_CLOCK_DIVIDER

This option specifies the divide value for the KV5X processor core clock from the system clock.

CONFIG_KV5X_FLASH_CLOCK_DIVIDER

This option specifies the divide value for the KV5X flash clock from the system clock.

CONFIG_KV5X_FLEXBUS_CLOCK_DIVIDER

This option specifies the divide value for the KV5X FlexBus clock from the system clock.

CONFIG_KW2XD_BUS_CLOCK_DIVIDER

This option specifies the divide value for the KW2xD bus clock from the system clock.

CONFIG_KW2XD_CORE_CLOCK_DIVIDER

This option specifies the divide value for the KW2xD processor core clock from the system clock.

CONFIG_KW2XD_FLASH_CLOCK_DIVIDER

This option specifies the divide value for the KW2xD flash clock from the system clock.

CONFIG_KW41_DBG_TRACE

The value depends on your debugging needs. This generates an encoded trace of events without going to debug logging to avoid timing impact on running code. The buffer is post analyzed via the debugger.

CONFIG_LAZY_FP_SHARING

This hidden option allows multiple threads to use the floating point registers, using logic to lazily save/restore the floating point register state on context switch.

On Intel Core processors, may be vulnerable to exploits which allows malware to read the contents of all floating point registers, see CVE-2018-3665.

CONFIG_LED

Include LED drivers in the system configuration.

CONFIG_LED_INIT_PRIORITY

System initialization priority for LED drivers.

CONFIG_LED_LOG_LEVEL

CONFIG_LED_LOG_LEVEL_DBG

Debug

CONFIG_LED_LOG_LEVEL_ERR

Error

CONFIG_LED_LOG_LEVEL_INF

Info

CONFIG_LED_LOG_LEVEL_OFF

Off

CONFIG_LED_LOG_LEVEL_WRN

Warning

CONFIG_LED_STRIP

Include LED strip drivers in the system configuration.

CONFIG_LED_STRIP_INIT_PRIORITY

System initialization priority for LED strip drivers.

CONFIG_LED_STRIP_LOG_LEVEL

CONFIG_LED_STRIP_LOG_LEVEL_DBG

Debug

CONFIG_LED_STRIP_LOG_LEVEL_ERR

Error

CONFIG_LED_STRIP_LOG_LEVEL_INF

Info

CONFIG_LED_STRIP_LOG_LEVEL_OFF

Off

CONFIG_LED_STRIP_LOG_LEVEL_WRN

Warning

CONFIG_LED_STRIP_RGB_SCRATCH

CONFIG_LEUART_GECKO

Enable the Gecko leuart driver.

CONFIG_LIBMETAL

This option enables the libmetal HAL abstraction layer

CONFIG_LIBMETAL_SRC_PATH

This option specifies the path to the source for the libmetal library

CONFIG_LIB_CPLUSPLUS

Link with STD C++ Library.

CONFIG_LINKER_ORPHAN_SECTION_ERROR

Linker exits with error when an orphan section is found.

CONFIG_LINKER_ORPHAN_SECTION_PLACE

Linker puts orphan sections in place without warnings or errors.

CONFIG_LINKER_ORPHAN_SECTION_WARN

Linker places the orphan sections in output and issues warning about those sections.

CONFIG_LINKER_SORT_BY_ALIGNMENT

This turns on the linker flag to sort sections by alignment in decreasing size of symbols. This helps to minimize padding between symbols.

CONFIG_LIS2DH

Enable SPI/I2C-based driver for LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12, LSM303AGR triaxial accelerometer sensors.

CONFIG_LIS2DH_ACCEL_RANGE_16G

+/-16g

CONFIG_LIS2DH_ACCEL_RANGE_2G

+/-2g

CONFIG_LIS2DH_ACCEL_RANGE_4G

+/-4g

CONFIG_LIS2DH_ACCEL_RANGE_8G

+/-8g

CONFIG_LIS2DH_ACCEL_RANGE_RUNTIME

Set at runtime

CONFIG_LIS2DH_ODR_1

1Hz

CONFIG_LIS2DH_ODR_2

10Hz

CONFIG_LIS2DH_ODR_3

25Hz

CONFIG_LIS2DH_ODR_4

50Hz

CONFIG_LIS2DH_ODR_5

100Hz

CONFIG_LIS2DH_ODR_6

200Hz

CONFIG_LIS2DH_ODR_7

400Hz

CONFIG_LIS2DH_ODR_8

1.6KHz

CONFIG_LIS2DH_ODR_9_LOW

5KHz

CONFIG_LIS2DH_ODR_9_NORMAL

1.25KHz

CONFIG_LIS2DH_ODR_RUNTIME

Set at runtime

CONFIG_LIS2DH_OPER_MODE_HIGH_RES

high resolution (12 bit)

CONFIG_LIS2DH_OPER_MODE_LOW_POWER

low power (8 bit)

CONFIG_LIS2DH_OPER_MODE_NORMAL

normal (10 bit)

CONFIG_LIS2DH_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DH_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DH_TRIGGER

CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DH_TRIGGER_NONE

No trigger

CONFIG_LIS2DH_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2DS12

Enable driver for LIS2DS12 accelerometer sensor driver

CONFIG_LIS2DS12_ENABLE_TEMP

Enable/disable temperature

CONFIG_LIS2DS12_FS

Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g

CONFIG_LIS2DS12_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 25Hz 3: 50Hz 4: 100Hz 5: 200Hz 6: 400Hz 7: 800Hz

CONFIG_LIS2DS12_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DS12_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DS12_TRIGGER

CONFIG_LIS2DS12_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DS12_TRIGGER_NONE

No trigger

CONFIG_LIS2DS12_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2DW12

Enable driver for LIS2DW12 accelerometer sensor driver

CONFIG_LIS2DW12_ACCEL_RANGE_16G

16G

CONFIG_LIS2DW12_ACCEL_RANGE_2G

2G

CONFIG_LIS2DW12_ACCEL_RANGE_4G

4G

CONFIG_LIS2DW12_ACCEL_RANGE_8G

8G

CONFIG_LIS2DW12_ACCEL_RANGE_RUNTIME

Set at runtime (Default 2G)

CONFIG_LIS2DW12_INT_PIN_1

int1

CONFIG_LIS2DW12_INT_PIN_2

int2

CONFIG_LIS2DW12_ODR_100

100 Hz

CONFIG_LIS2DW12_ODR_12_5

12.5 Hz

CONFIG_LIS2DW12_ODR_1600

1600 Hz

CONFIG_LIS2DW12_ODR_1_6

1.6 Hz

CONFIG_LIS2DW12_ODR_200

200 Hz

CONFIG_LIS2DW12_ODR_25

25 Hz

CONFIG_LIS2DW12_ODR_400

400 Hz

CONFIG_LIS2DW12_ODR_50

50 Hz

CONFIG_LIS2DW12_ODR_800

800 Hz

CONFIG_LIS2DW12_ODR_RUNTIME

Set at runtime (Default 100 Hz)

CONFIG_LIS2DW12_ONLY_SINGLE

single

CONFIG_LIS2DW12_POWER_MODE

Specify the sensor power mode 0: Low Power M1 1: Low Power M2 2: Low Power M3 3: Low Power M4 4: High Performance

CONFIG_LIS2DW12_PULSE

Enable pulse (single/double tap) detection

CONFIG_LIS2DW12_PULSE_LTNCY

When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR.

CONFIG_LIS2DW12_PULSE_QUIET

Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. Where 0 equals 2*1/ODR and 1LSB = 4*1/ODR.

CONFIG_LIS2DW12_PULSE_SHOCK

Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. Where 0 equals 4*1/ODR and 1LSB = 8*1/ODR.

CONFIG_LIS2DW12_PULSE_THSX

Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_THSY

Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_THSZ

Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_X

Enable X axis for pulse

CONFIG_LIS2DW12_PULSE_Y

Enable Y axis for pulse

CONFIG_LIS2DW12_PULSE_Z

Enable Z axis for pulse

CONFIG_LIS2DW12_SINGLE_DOUBLE

single/double

CONFIG_LIS2DW12_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DW12_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DW12_TRIGGER

CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DW12_TRIGGER_NONE

No trigger

CONFIG_LIS2DW12_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2MDL

Enable driver for LIS2MDL I2C-based magnetometer sensor.

CONFIG_LIS2MDL_MAG_ODR_RUNTIME

Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz)

CONFIG_LIS2MDL_SPI_FULL_DUPLEX

Enable SPI 4wire mode (separated MISO and MOSI lines)

CONFIG_LIS2MDL_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2MDL_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2MDL_TRIGGER

CONFIG_LIS2MDL_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2MDL_TRIGGER_NONE

No trigger

CONFIG_LIS2MDL_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS3MDL

Enable driver for LIS3MDL I2C-based magnetometer.

CONFIG_LIS3MDL_FS

Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 4, 8, 12 and 16.

CONFIG_LIS3MDL_ODR

Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.625, 1.25, 2.5, 5, 10, 20, 40, 80, 155, 300, 560 and 1000.

CONFIG_LIS3MDL_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS3MDL_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS3MDL_TRIGGER

CONFIG_LIS3MDL_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS3MDL_TRIGGER_NONE

No trigger

CONFIG_LIS3MDL_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LITEX_TIMER

This module implements a kernel device driver for LiteX Timer.

CONFIG_LLMNR_RESOLVER

This option enables link local multicast name resolution client side support. See RFC 4795 for details. LLMNR is typically used by Windows hosts. If you enable this option, then the DNS requests are ONLY sent to LLMNR well known multicast address 224.0.0.252:5355 or [ff02::1:3]:5355 and other DNS server addresses are ignored.

CONFIG_LLMNR_RESOLVER_ADDITIONAL_BUF_CTR

Number of additional buffers available for the LLMNR responder.

CONFIG_LLMNR_RESPONDER

This option enables the LLMNR responder support for Zephyr. It will listen well-known address ff02::1:3 and 224.0.0.252. Currently this only returns IP address information. You must set CONFIG_NET_HOSTNAME to some meaningful value and then LLMNR will start to respond to <hostname> LLMNR queries. Note that LLMNR queries should only contain single-label names so there should be NO dot (“.”) in the name (RFC 4795 ch 3). Current implementation does not support TCP. See RFC 4795 for more details about LLMNR.

CONFIG_LLMNR_RESPONDER_INIT_PRIO

Note that if NET_CONFIG_AUTO_INIT is enabled, then this value should be bigger than its value.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_DBG

Write to log with NET_DBG or LOG_DBG in addition to previous levels.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_DEFAULT

Use default log level.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_ERR

Only write to log when NET_ERR or LOG_ERR is used.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_INF

Write to log with NET_INFO or LOG_INF in addition to previous levels.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_OFF

Do not write to log.

CONFIG_LLMNR_RESPONDER_LOG_LEVEL_WRN

Write to log with NET_WARN or LOG_WRN in addition to previous level.

CONFIG_LLMNR_RESPONDER_TTL

DNS answers will use the TTL (in seconds). A default value is 30 seconds as recommended by RFC 4795 chapter 2.8