controller.h

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/*
 * Copyright (c) 2021 BayLibre, SAS
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
 
#include <zephyr/types.h>
#include <device.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef uint32_t (*pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf,
                                          unsigned int reg);
 
typedef void (*pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf,
                                          unsigned int reg, uint32_t data);
 
typedef bool (*pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf,
                                            bool mem, bool mem64, size_t bar_size,
                                            uintptr_t *bar_bus_addr);
 
typedef bool (*pcie_ctrl_region_get_allocate_base_t)(const struct device *dev, pcie_bdf_t bdf,
                                                     bool mem, bool mem64, size_t align,
                                                     uintptr_t *bar_base_addr);
 
typedef bool (*pcie_ctrl_region_translate_t)(const struct device *dev, pcie_bdf_t bdf,
                                             bool mem, bool mem64, uintptr_t bar_bus_addr,
                                             uintptr_t *bar_addr);
 
uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg);
 
 
void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
                                  unsigned int reg, uint32_t data);
 
void pcie_generic_ctrl_enumerate(const struct device *dev, pcie_bdf_t bdf_start);
 
__subsystem struct pcie_ctrl_driver_api {
        pcie_ctrl_conf_read_t conf_read;
        pcie_ctrl_conf_write_t conf_write;
        pcie_ctrl_region_allocate_t region_allocate;
        pcie_ctrl_region_get_allocate_base_t region_get_allocate_base;
        pcie_ctrl_region_translate_t region_translate;
};
 
static inline uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf,
                                           unsigned int reg)
{
        const struct pcie_ctrl_driver_api *api =
                (const struct pcie_ctrl_driver_api *)dev->api;
 
        return api->conf_read(dev, bdf, reg);
}
 
static inline void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf,
                                        unsigned int reg, uint32_t data)
{
        const struct pcie_ctrl_driver_api *api =
                (const struct pcie_ctrl_driver_api *)dev->api;
 
        api->conf_write(dev, bdf, reg, data);
}
 
static inline bool pcie_ctrl_region_allocate(const struct device *dev, pcie_bdf_t bdf,
                                             bool mem, bool mem64, size_t bar_size,
                                             uintptr_t *bar_bus_addr)
{
        const struct pcie_ctrl_driver_api *api =
                (const struct pcie_ctrl_driver_api *)dev->api;
 
        return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr);
}
 
static inline bool pcie_ctrl_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf,
                                                      bool mem, bool mem64, size_t align,
                                                      uintptr_t *bar_base_addr)
{
        const struct pcie_ctrl_driver_api *api =
                (const struct pcie_ctrl_driver_api *)dev->api;
 
        return api->region_get_allocate_base(dev, bdf, mem, mem64, align, bar_base_addr);
}
 
static inline bool pcie_ctrl_region_translate(const struct device *dev, pcie_bdf_t bdf,
                                          bool mem, bool mem64, uintptr_t bar_bus_addr,
                                          uintptr_t *bar_addr)
{
        const struct pcie_ctrl_driver_api *api =
                (const struct pcie_ctrl_driver_api *)dev->api;
 
        if (!api->region_translate) {
                *bar_addr = bar_bus_addr;
                return true;
        } else {
                return api->region_translate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr);
        }
}
 
struct pcie_ctrl_config {
        /* Configuration space physical address */
        uintptr_t cfg_addr;
        /* Configuration space physical size */
        size_t cfg_size;
        /* BAR regions translation ranges count */
        size_t ranges_count;
        /* BAR regions translation ranges table */
        struct {
                /* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
                uint32_t flags;
                /* bus-centric offset from the start of the region */
                uintptr_t pcie_bus_addr;
                /* CPU-centric offset from the start of the region */
                uintptr_t host_map_addr;
                /* region size */
                size_t map_length;
        } ranges[];
};
 
/*
 * Fills the pcie_ctrl_config.ranges table from DT
 */
#define PCIE_RANGE_FORMAT(node_id, idx)                                                 \
{                                                                                       \
        .flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx),                        \
        .pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx),              \
        .host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx),             \
        .map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx),                            \
},
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_ */