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3.0.0
A Scalable Open Source RTOS
3.0.0
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esp32c3_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
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/* System Clock Source */
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#define ESP32_CLK_SRC_XTAL 0U
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#define ESP32_CLK_SRC_PLL 1U
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#define ESP32_CLK_SRC_RTC8M 2U
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#define ESP32_CLK_SRC_APLL 3U
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/* Supported CPU Frequencies */
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#define ESP32_CLK_CPU_80M 80U
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#define ESP32_CLK_CPU_160M 160U
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/* Supported XTAL Frequencies */
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#define ESP32_CLK_XTAL_32M 0U
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#define ESP32_CLK_XTAL_40M 1U
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/* Modules IDs
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* These IDs are actually offsets in CLK and RST Control registers.
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* These IDs shouldn't be changed unless there is a Hardware change
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* from Espressif.
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*
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* Basic Modules
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* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
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*/
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#define ESP32_LEDC_MODULE 0
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#define ESP32_UART0_MODULE 1
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#define ESP32_UART1_MODULE 2
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#define ESP32_USB_MODULE 3
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#define ESP32_I2C0_MODULE 4
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#define ESP32_I2S1_MODULE 5
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#define ESP32_TIMG0_MODULE 6
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#define ESP32_TIMG1_MODULE 7
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#define ESP32_UHCI0_MODULE 8
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#define ESP32_RMT_MODULE 9
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#define ESP32_SPI_MODULE 10
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#define ESP32_SPI2_MODULE 11
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#define ESP32_TWAI_MODULE 12
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#define ESP32_RNG_MODULE 13
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#define ESP32_WIFI_MODULE 14
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#define ESP32_BT_MODULE 15
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#define ESP32_WIFI_BT_COMMON_MODULE 16
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#define ESP32_BT_BASEBAND_MODULE 17
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#define ESP32_BT_LC_MODULE 18
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#define ESP32_RSA_MODULE 19
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#define ESP32_AES_MODULE 20
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#define ESP32_SHA_MODULE 21
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#define ESP32_HMAC_MODULE 22
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#define ESP32_DS_MODULE 23
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#define ESP32_GDMA_MODULE 24
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#define ESP32_SYSTIMER_MODULE 25
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#define ESP32_SARADC_MODULE 26
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#define ESP32_MODULE_MAX 27
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ */
include
dt-bindings
clock
esp32c3_clock.h
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