Zephyr API Documentation  3.0.0
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esp32c3_clock.h
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1/*
2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
9
10/* System Clock Source */
11#define ESP32_CLK_SRC_XTAL 0U
12#define ESP32_CLK_SRC_PLL 1U
13#define ESP32_CLK_SRC_RTC8M 2U
14#define ESP32_CLK_SRC_APLL 3U
15
16/* Supported CPU Frequencies */
17#define ESP32_CLK_CPU_80M 80U
18#define ESP32_CLK_CPU_160M 160U
19
20/* Supported XTAL Frequencies */
21#define ESP32_CLK_XTAL_32M 0U
22#define ESP32_CLK_XTAL_40M 1U
23
24/* Modules IDs
25 * These IDs are actually offsets in CLK and RST Control registers.
26 * These IDs shouldn't be changed unless there is a Hardware change
27 * from Espressif.
28 *
29 * Basic Modules
30 * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
31 */
32#define ESP32_LEDC_MODULE 0
33#define ESP32_UART0_MODULE 1
34#define ESP32_UART1_MODULE 2
35#define ESP32_USB_MODULE 3
36#define ESP32_I2C0_MODULE 4
37#define ESP32_I2S1_MODULE 5
38#define ESP32_TIMG0_MODULE 6
39#define ESP32_TIMG1_MODULE 7
40#define ESP32_UHCI0_MODULE 8
41#define ESP32_RMT_MODULE 9
42#define ESP32_SPI_MODULE 10
43#define ESP32_SPI2_MODULE 11
44#define ESP32_TWAI_MODULE 12
45#define ESP32_RNG_MODULE 13
46#define ESP32_WIFI_MODULE 14
47#define ESP32_BT_MODULE 15
48#define ESP32_WIFI_BT_COMMON_MODULE 16
49#define ESP32_BT_BASEBAND_MODULE 17
50#define ESP32_BT_LC_MODULE 18
51#define ESP32_RSA_MODULE 19
52#define ESP32_AES_MODULE 20
53#define ESP32_SHA_MODULE 21
54#define ESP32_HMAC_MODULE 22
55#define ESP32_DS_MODULE 23
56#define ESP32_GDMA_MODULE 24
57#define ESP32_SYSTIMER_MODULE 25
58#define ESP32_SARADC_MODULE 26
59#define ESP32_MODULE_MAX 27
60
61#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ */