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LiteX VexRiscv

LiteX VexRiscv is an example of a system on a chip (SoC) that consists of a VexRiscv processor and additional peripherals. This setup can be generated using Zephyr on LiteX VexRiscv (reference platform) or LiteX SoC Builder and can be used on various FPGA chips. The bitstream (FPGA configuration file) can be obtained using both vendor-specific and open-source tools, including the F4PGA toolchain.

The litex_vexriscv board configuration in Zephyr is meant for the LiteX VexRiscv SoC implementation generated for the Digilent Arty A7-35T or A7-100T Development Boards or SDI-MIPI Video Converter.

LiteX is based on Migen/MiSoC SoC builder and provides ready-made system components such as buses, streams, interconnects, common cores, and CPU wrappers to create SoCs easily. The tool contains mechanisms for integrating, simulating, and building various designs that target multiple chips of different vendors. More information about the LiteX project can be found on LiteX’s website.

VexRiscv is a 32-bit implementation of the RISC-V CPU architecture written in the SpinalHDL. The processor supports M, C, and A RISC-V instruction set extensions, with numerous optimizations that include multistage pipelines and data caching. The project provides many optional extensions that can be used to customize the design (JTAG, MMU, MUL/DIV extensions). The implementation is optimized for FPGA chips. More information about the project can be found on VexRiscv’s website.

To run the ZephyrOS on the VexRiscv CPU, it is necessary to prepare the bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achieved using the Zephyr on LiteX VexRiscv reference platform. You can also use the official LiteX SoC Builder.

Bitstream generation

Zephyr on LiteX VexRiscv

Using this platform ensures that all registers addresses are in the proper place. All drivers were tested using this platform. In order to generate the bitstream, proceed with the following instruction:

1. Clone the repository and update all submodules:

   git clone https://github.com/litex-hub/zephyr-on-litex-vexriscv.git
   cd zephyr-on-litex-vexriscv
   git submodule update --init --recursive
   

   Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. It can be done by following instructions in this tutorial.

   In order to generate the bitstream for the SDI-MIPI Video Converter, install oxide (yosys+nextpnr) toolchain by following these instructions.

2. Next, get all required packages and run the install script:

   apt-get install build-essential bzip2 python3 python3-dev python3-pip
   ./install.sh
   

3. Add LiteX to path:

   source ./init
   

4. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):

   export F4PGA_INSTALL_DIR=~/opt/f4pga
   export FPGA_FAM="xc7"
   export PATH="$F4PGA_INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
   source "$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh"
   conda activate $FPGA_FAM
   

5. Generate the bitstream for the Arty 35T:

   ./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
   

6. Generate the bitstream for the Arty 100T:

   ./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
   

7. Generate the bitstream for the SDI-MIPI Video Converter:

   ./make.py --board=sdi_mipi_bridge --build --toolchain=oxide
   

Official LiteX SoC builder

You can also generate the bitstream using the official LiteX repository. In that case you must also generate a dts overlay.

1. Install Migen/LiteX and the LiteX’s cores:

   wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
   chmod +x litex_setup.py
   ./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)
   

2. Install the RISC-V toolchain:

   pip3 install meson ninja
   ./litex_setup.py --gcc=riscv
   

3. Build the target:

   ./litex-boards/litex_boards/targets/digilent_arty.py --build --timer-uptime --csr-json csr.json
   

4. Generate the dts and config overlay:

   ./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
   

Programming and booting

Building

Applications for the litex_vexriscv board configuration can be built as usual (see Building an Application). In order to build the application for litex_vexriscv, set the BOARD variable to litex_vexriscv.

If you were generating bitstream with the official LiteX SoC builder you need to pass an additional argument:

west build -b litex_vexriscv path/to/app -DDTC_OVERLAY_FILE=path/to/overlay.dts

Booting

To upload the bitstream to Digilent Arty A7-35 you can use xc3sprog or openFPGALoader:

xc3sprog -c nexys4 digilent_arty.bit

openFPGALoader -b arty_a7_100t digilent_arty.bit

Use ecpprog to upload the bitstream to SDI-MIPI Video Converter:

ecpprog -S antmicro_sdi_mipi_video_converter.bit

You can boot from a serial port using litex_term (replace ttyUSBX with your device) , e.g.:

litex_term /dev/ttyUSBX --speed 115200 --kernel zephyr.bin