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st,stm32f4-pll-clock

Vendor: STMicroelectronics

Description

STM32F4 Main PLL node binding:

Takes one of clk_hse or clk_hsi as input clock, with an
input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
in this acceptable range.

Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:

  f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
  f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 80 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Division factor for the PLL input clock
Valid range: 2 - 63

This property is required.

mul-n

int

 
Main PLL multiplication factor for VCO
Valid range: 50 - 432

This property is required.

div-p

int

 
Main PLL division factor for PLLSAI2CLK

This property is required.

Legal values: 2, 4, 6, 8

div-q

int

 
Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
generator clocks.
Valid range: 2 - 15

div-r

int

 
Main PLL (PLL) division factor for I2S and DFSDM
generator clocks.
Valid range: 2 - 7