gd,gd32-dma-v1
Vendor: GigaDevice Semiconductor
Description
These nodes are “dma” bus nodes.
GD32 DMA controller with FIFO
channel: Select channel for data transmitting
slot: Select peripheral to connect DMA
config: A 32bit mask specifying the DMA channel configuration
- bit 6-7: Direction (see dma.h)
- 0x0: MEMORY to MEMORY
- 0x1: MEMORY to PERIPH
- 0x2: PERIPH to MEMORY
- 0x3: reserved for PERIPH to PERIPH
- bit 9: Peripheral address increase
- 0x0: no address increment between transfers
- 0x1: increment address between transfers
- bit 10: Memory address increase
- 0x0: no address increase between transfers
- 0x1: increase address between transfers
- bit 11-12: Peripheral data width
- 0x0: 8 bits
- 0x1: 16 bits
- 0x2: 32 bits
- 0x3: reserved
- bit 13-14: Memory data width
- 0x0: 8 bits
- 0x1: 16 bits
- 0x2: 32 bits
- 0x3: reserved
- bit 15: Peripheral Increment Offset Size
- 0x0: offset size is linked to the peripheral bus width
- 0x1: offset size is fixed to 4 (32-bit alignment)
- bit 16-17: Priority
- 0x0: low
- 0x1: medium
- 0x2: high
- 0x3: very high
fifo-threshold: A 32bit bitfield value specifying FIFO threshold
- bit 0-1: Depth of DMA's FIFO used by burst-transfer.
- 0x0: 1 word
- 0x1: 2 word
- 0x2: 3 word
- 0x3: 4 word
Example of devicetree configuration
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
dmas = <&dma1 0 3 0 0>, <&dma1 5 3 GD32_DMA_PRIORITY_HIGH 0>
dma-names = "rx", "tx";
};
"spi0" uses dma1 for transmitting and receiving in the example.
Each is named "rx" and "tx".
The first cell assigns channel 0 to receive and channel 5 to transmit.
The second cell is slot. Both channels select 3.
What the slot number '3' means depends on the DMA controller and channel.
See the Hardware manual.
The config that places on the third can take various configs.
But the setting used depends on each driver implementation.
Set the priority for the transmitting channel as HIGH, LOW(the default) for receive channel.
The fifo-threshold cell that places the fourth is configuring FIFO threshold.
The behavior of burst transfer determines by data-width in the config cell,
burst-length in the dma_config struct, and fifo-threshold.
A single burst transfer transfers [(4 * fifo-threshold)] bytes using with DMA's FIFO.
Where (data-width * burst-length) must be multiple numbers of burst transfer size.
For example, In the case of data-width is 'byte' and burst-length is 8.
If the fifo-threshold is a 2-word case, it runs one burst transfer to transfer 8 bytes.
Or the fifo-threshold is a 4-word case, runs two times burst transfer to transferring 8 bytes each
time.
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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Reset information
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Name of each reset
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Number of items to expect in a DMA specifier
This property is required. Constant value: |
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Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.
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Number of DMA channels supported by the controller
This property is required. |
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Number of DMA request signals supported by the controller.
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Memory address alignment requirement for DMA buffers used by the controller.
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Memory size alignment requirement for DMA buffers used by the controller.
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Minimal chunk of data possible to be copied by the controller.
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The DMA controller supporting memory to memory transfer
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Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “gd,gd32-dma-v1” compatible.
Name |
Type |
Details |
|---|---|---|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
This property is required. See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
This property is required. |
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Specifier cell names
dma cells: channel, slot, config, fifo-threshold