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jedec,spi-nor (on spi bus)

Vendor: JEDEC Solid State Technology Association

Description

Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI
API) control of serial flash memories using the standard M25P80-based
command set.

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
supply-gpios	phandle-array	GPIO specifier that controls power to the device. This property should be provided when the device has a dedicated switch that controls power to the device. The supply state is entirely the responsibility of the device driver. Contrast with vin-supply.
vin-supply	phandle	Reference to the regulator that controls power to the device. The referenced devicetree node must have a regulator compatible. This property should be provided when device power is supplied by a shared regulator. The supply state is dependent on the request status of all devices fed by the regulator. Contrast with supply-gpios. If both properties are provided then the regulator must be requested before the supply GPIOS is set to an active state, and the supply GPIOS must be set to an inactive state before releasing the regulator.
spi-max-frequency	int	Maximum clock frequency of device's SPI interface in Hz This property is required.
duplex	int	Duplex mode, full or half. By default it's always full duplex thus 0 as this is, by far, the most common mode. Use the macros not the actual enum value, here is the concordance list (see dt-bindings/spi/spi.h) 0 SPI_FULL_DUPLEX 2048 SPI_HALF_DUPLEX Legal values: 0, 2048
frame-format	int	Motorola or TI frame format. By default it's always Motorola's, thus 0 as this is, by far, the most common format. Use the macros not the actual enum value, here is the concordance list (see dt-bindings/spi/spi.h) 0 SPI_FRAME_FORMAT_MOTOROLA 32768 SPI_FRAME_FORMAT_TI Legal values: 0, 32768
spi-cpol	boolean	SPI clock polarity which indicates the clock idle state. If it is used, the clock idle state is logic high; otherwise, low.
spi-cpha	boolean	SPI clock phase that indicates on which edge data is sampled. If it is used, data is sampled on the second edge; otherwise, on the first edge.
spi-hold-cs	boolean	In some cases, it is necessary for the master to manage SPI chip select under software control, so that multiple spi transactions can be performed without releasing it. A typical use case is variable length SPI packets where the first spi transaction reads the length and the second spi transaction reads length bytes.
jedec-id	uint8-array	JEDEC ID as manufacturer ID, memory type, memory density
size	int	flash capacity in bits
sfdp-bfp	uint8-array	Contains the 32-bit words in little-endian byte order from the JESD216 Serial Flash Discoverable Parameters Basic Flash Parameters table. This provides flash-specific configuration information in cases were runtime retrieval of SFDP data is not desired.
quad-enable-requirements	string	Quad Enable Requirements value from JESD216 BFP DW15. Use NONE if the device detects 1-1-4 and 1-4-4 modes by the instruction. Use S1B6 if QE is bit 6 of the first status register byte, and can be configured by reading then writing one byte with RDSR and WRSR. For other fields see the specification. Legal values: 'NONE', 'S2B1v1', 'S1B6', 'S2B7', 'S2B1v4', 'S2B1v5', 'S2B1v6'
enter-4byte-addr	int	Enter 4-Byte Addressing value from JESD216 BFP DW16 This property is ignored if the device is configured to use SFDP data from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME). For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24 of DW16 identifying ways a device can be placed into 4-byte addressing mode. If provided as a non-zero value the driver assumes that 4-byte addressing is require to access the full address range, and automatically puts the device into 4-byte address mode when the device is initialized.
page-size	int	Number of bytes in a page from JESD216 BFP DW11 This property is only used in the CONFIG_SPI_NOR_SFDP_MINIMAL configuration. It is ignored if the device is configured to use SFDP data from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or if the SFDP parameters are read from the device at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME). The default value is 256 bytes if the value is not specified.
requires-ulbpr	boolean	Indicates the device requires the ULBPR (0x98) command. Some flash chips such as the Microchip SST26VF series have a block protection register that initializes to write-protected. Use this property to indicate that the BPR must be unlocked before write operations can proceed.
has-dpd	boolean	Indicates the device supports the DPD (0xB9) command. Use this property to indicate the flash chip supports the Deep Power-Down mode that is entered by command 0xB9 to reduce power consumption below normal standby levels. Use of this property implies that the RDPD (0xAB) Release from Deep Power Down command is also supported. (On some chips this command functions as Read Electronic Signature; see t-enter-dpd).
dpd-wakeup-sequence	array	Specifies wakeup durations for devices without RDPD. Some devices (Macronix MX25R in particular) wake from deep power down by a timed sequence of CSn toggles rather than the RDPD command. This property specifies three durations measured in nanoseconds, in this order: (1) tDPDD (Delay Time for Release from Deep Power-Down Mode) (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode) (3) tRDP (Recovery Time for Release from Deep Power-Down Mode) Absence of this property indicates that the RDPD command should be used to wake the chip from Deep Power-Down mode.
t-enter-dpd	int	Duration required to complete the DPD command. This provides the duration, in nanoseconds, that CSn must be remain deasserted after issuing DPD before the chip will enter deep power down. If not provided the driver does not enforce a delay.
t-exit-dpd	int	Duration required to complete the RDPD command. This provides the duration, in nanoseconds, that CSn must be remain deasserted after issuing RDPD before the chip will exit deep power down and be ready to receive additional commands. If not provided the driver does not enforce a delay.
has-lock	int	Bit mask of bits of the status register that should be cleared on startup. Some devices from certain vendors power-up with block protect bits set in the status register, which prevent any erase or program operation from working. Devices that have this behavior need to clear those bits on startup. However, other devices have non-volatile bits in the status register that should not be cleared. This value, when present, identifies bits in the status register that should be cleared when the device is initialized.
mxicy,mx25r-power-mode	string	Select to configure flash to use ultra low power mode or high performance mode (L/H switch). The high performance mode has faster write and erase performance, but use more power than ultra low power mode. Only supported on Macronix MX25R Ultra Low Power series. Legal values: 'low-power', 'high-performance'
wp-gpios	phandle-array	WPn pin
hold-gpios	phandle-array	HOLDn pin
reset-gpios	phandle-array	RESETn pin