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espressif,esp32-spi

Vendor: Espressif Systems

Description

These nodes are “spi” bus nodes.

ESP32 SPI

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

This property is required.

half-duplex

boolean

 
Enable half-duplex communication mode.

Transmit data before receiving it, instead of simultaneously

dummy-comp

boolean

 
Enable dummy SPI compensation cycles

sio

boolean

 
Enable 3-wire mode

Use MOSI for both sending and receiving data

dma-enabled

boolean

 
Enable SPI DMA support

dma-clk

int

 
DMA clock source

dma-host

int

 
DMA Host - 0 -> SPI2, 1 -> SPI3

clk-as-cs

boolean

 
Support to toggle the CS while the clock toggles

Output clock on CS line if CS is active

positive-cs

boolean

 
Make CS positive during a transaction instead of negative

use-iomux

boolean

 
Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX
routing mechanism instead, this avoids extra routing latency and makes
possible the use of operating frequencies higher than 20 MHz.

Refer to SoC's Technical Reference Manual to check which pins are
allowed to use this routing path.

cs-setup-time

int

 
Chip select setup time setting, see TRF for SOC for details of
timing applied.

cs-hold-time

int

 
Chip select hold time setting, see TRF for SOC for details of
timing applied.

line-idle-low

boolean

 
Default MISO and MOSI pins GPIO level when idle. Defaults to high by default.