Zephyr API Documentation
3.7.0
A Scalable Open Source RTOS
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imx_ccm_rev2.h
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/*
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* Copyright 2021,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
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/* Peripheral:
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* range: 0 - 0xFF, starting from 0
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*
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* Instance:
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* range: 0 - 0xFF, starting from 0
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*/
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#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
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#define IMX_CCM_INSTANCE_MASK 0xFFUL
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#define IMX_CCM_CORESYS_CLK 0
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#define IMX_CCM_PLATFORM_CLK 0x1UL
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#define IMX_CCM_BUS_CLK 0x2UL
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/* LPUART */
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#define IMX_CCM_LPUART_CLK 0x300UL
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#define IMX_CCM_LPUART1_CLK 0x300UL
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#define IMX_CCM_LPUART2_CLK 0x301UL
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#define IMX_CCM_LPUART3_CLK 0x302UL
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#define IMX_CCM_LPUART4_CLK 0x303UL
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#define IMX_CCM_LPUART5_CLK 0x304UL
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#define IMX_CCM_LPUART6_CLK 0x305UL
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#define IMX_CCM_LPUART7_CLK 0x306UL
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#define IMX_CCM_LPUART8_CLK 0x307UL
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#define IMX_CCM_LPUART9_CLK 0x308UL
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#define IMX_CCM_LPUART10_CLK 0x309UL
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#define IMX_CCM_LPUART11_CLK 0x30aUL
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#define IMX_CCM_LPUART12_CLK 0x30bUL
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/* LPI2C */
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#define IMX_CCM_LPI2C_CLK 0x400UL
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#define IMX_CCM_LPI2C1_CLK 0x400UL
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#define IMX_CCM_LPI2C2_CLK 0x401UL
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#define IMX_CCM_LPI2C3_CLK 0x402UL
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#define IMX_CCM_LPI2C4_CLK 0x403UL
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#define IMX_CCM_LPI2C5_CLK 0x404UL
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#define IMX_CCM_LPI2C6_CLK 0x405UL
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#define IMX_CCM_LPI2C7_CLK 0x406UL
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#define IMX_CCM_LPI2C8_CLK 0x407UL
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/* LPSPI */
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#define IMX_CCM_LPSPI_CLK 0x500UL
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#define IMX_CCM_LPSPI1_CLK 0x500UL
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#define IMX_CCM_LPSPI2_CLK 0x501UL
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#define IMX_CCM_LPSPI3_CLK 0x502UL
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#define IMX_CCM_LPSPI4_CLK 0x503UL
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#define IMX_CCM_LPSPI5_CLK 0x504UL
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#define IMX_CCM_LPSPI6_CLK 0x505UL
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#define IMX_CCM_LPSPI7_CLK 0x506UL
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#define IMX_CCM_LPSPI8_CLK 0x507UL
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/* USDHC */
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#define IMX_CCM_USDHC1_CLK 0x600UL
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#define IMX_CCM_USDHC2_CLK 0x601UL
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/* DMA */
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#define IMX_CCM_EDMA_CLK 0x700UL
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#define IMX_CCM_EDMA_LPSR_CLK 0x701UL
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/* PWM */
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#define IMX_CCM_PWM_CLK 0x800UL
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/* CAN */
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#define IMX_CCM_CAN_CLK 0x900UL
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#define IMX_CCM_CAN1_CLK 0x900UL
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#define IMX_CCM_CAN2_CLK 0x901UL
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#define IMX_CCM_CAN3_CLK 0x902UL
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/* GPT */
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#define IMX_CCM_GPT_CLK 0x1000UL
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#define IMX_CCM_GPT1_CLK 0x1000UL
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#define IMX_CCM_GPT2_CLK 0x1001UL
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#define IMX_CCM_GPT3_CLK 0x1002UL
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#define IMX_CCM_GPT4_CLK 0x1003UL
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#define IMX_CCM_GPT5_CLK 0x1004UL
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#define IMX_CCM_GPT6_CLK 0x1005UL
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/* SAI */
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#define IMX_CCM_SAI1_CLK 0x1100UL
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#define IMX_CCM_SAI2_CLK 0x1101UL
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#define IMX_CCM_SAI3_CLK 0x1102UL
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#define IMX_CCM_SAI4_CLK 0x1103UL
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/* ENET */
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#define IMX_CCM_ENET_CLK 0x1200UL
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#define IMX_CCM_ENET_PLL 0x1201UL
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#define IMX_CCM_ENET1G_CLK 0x1202UL
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#define IMX_CCM_ENET1G_PLL 0x1203UL
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/* FLEXSPI */
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#define IMX_CCM_FLEXSPI_CLK 0x1300UL
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#define IMX_CCM_FLEXSPI2_CLK 0x1301UL
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/* PIT */
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#define IMX_CCM_PIT_CLK 0x1400UL
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#define IMX_CCM_PIT1_CLK 0x1401UL
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/* ADC */
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#define IMX_CCM_LPADC1_CLK 0x1500UL
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#define IMX_CCM_LPADC2_CLK 0x1501UL
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/* TPM */
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#define IMX_CCM_TPM_CLK 0x1600UL
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#define IMX_CCM_TPM1_CLK 0x1600UL
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#define IMX_CCM_TPM2_CLK 0x1601UL
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#define IMX_CCM_TPM3_CLK 0x1602UL
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#define IMX_CCM_TPM4_CLK 0x1603UL
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#define IMX_CCM_TPM5_CLK 0x1604UL
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#define IMX_CCM_TPM6_CLK 0x1605UL
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/* QTMR */
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#define IMX_CCM_QTMR_CLK 0x6000UL
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#define IMX_CCM_QTMR1_CLK 0x6000UL
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#define IMX_CCM_QTMR2_CLK 0x6001UL
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#define IMX_CCM_QTMR3_CLK 0x6002UL
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#define IMX_CCM_QTMR4_CLK 0x6003UL
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */
zephyr
dt-bindings
clock
imx_ccm_rev2.h
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