Zephyr API Documentation
3.7.0
A Scalable Open Source RTOS
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nxp_s32k344_clock.h
Go to the documentation of this file.
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_
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#define NXP_S32_FIRC_CLK 1U
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#define NXP_S32_FIRC_STANDBY_CLK 2U
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#define NXP_S32_SIRC_CLK 3U
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#define NXP_S32_SIRC_STANDBY_CLK 4U
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#define NXP_S32_FXOSC_CLK 5U
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#define NXP_S32_SXOSC_CLK 6U
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#define NXP_S32_PLL_CLK 7U
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#define NXP_S32_PLL_POSTDIV_CLK 8U
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#define NXP_S32_PLL_PHI0_CLK 9U
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#define NXP_S32_PLL_PHI1_CLK 10U
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#define NXP_S32_EMAC_MII_RX_CLK 11U
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#define NXP_S32_EMAC_MII_RMII_TX_CLK 12U
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#define NXP_S32_SCS_CLK 13U
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#define NXP_S32_CORE_CLK 14U
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#define NXP_S32_AIPS_PLAT_CLK 15U
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#define NXP_S32_AIPS_SLOW_CLK 16U
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#define NXP_S32_HSE_CLK 17U
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#define NXP_S32_DCM_CLK 18U
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#define NXP_S32_LBIST_CLK 19U
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#define NXP_S32_QSPI_MEM_CLK 20U
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#define NXP_S32_CLKOUT_RUN_CLK 21U
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#define NXP_S32_ADC0_CLK 23U
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#define NXP_S32_ADC1_CLK 24U
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#define NXP_S32_ADC2_CLK 25U
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#define NXP_S32_BCTU0_CLK 26U
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#define NXP_S32_CLKOUT_STANDBY_CLK 27U
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#define NXP_S32_CMP0_CLK 28U
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#define NXP_S32_CMP1_CLK 29U
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#define NXP_S32_CMP2_CLK 30U
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#define NXP_S32_CRC0_CLK 31U
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#define NXP_S32_DCM0_CLK 32U
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#define NXP_S32_DMAMUX0_CLK 33U
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#define NXP_S32_DMAMUX1_CLK 34U
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#define NXP_S32_EDMA0_CLK 35U
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#define NXP_S32_EDMA0_TCD0_CLK 36U
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#define NXP_S32_EDMA0_TCD1_CLK 37U
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#define NXP_S32_EDMA0_TCD2_CLK 38U
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#define NXP_S32_EDMA0_TCD3_CLK 39U
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#define NXP_S32_EDMA0_TCD4_CLK 40U
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#define NXP_S32_EDMA0_TCD5_CLK 41U
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#define NXP_S32_EDMA0_TCD6_CLK 42U
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#define NXP_S32_EDMA0_TCD7_CLK 43U
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#define NXP_S32_EDMA0_TCD8_CLK 44U
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#define NXP_S32_EDMA0_TCD9_CLK 45U
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#define NXP_S32_EDMA0_TCD10_CLK 46U
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#define NXP_S32_EDMA0_TCD11_CLK 47U
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#define NXP_S32_EDMA0_TCD12_CLK 48U
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#define NXP_S32_EDMA0_TCD13_CLK 49U
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#define NXP_S32_EDMA0_TCD14_CLK 50U
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#define NXP_S32_EDMA0_TCD15_CLK 51U
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#define NXP_S32_EDMA0_TCD16_CLK 52U
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#define NXP_S32_EDMA0_TCD17_CLK 53U
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#define NXP_S32_EDMA0_TCD18_CLK 54U
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#define NXP_S32_EDMA0_TCD19_CLK 55U
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#define NXP_S32_EDMA0_TCD20_CLK 56U
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#define NXP_S32_EDMA0_TCD21_CLK 57U
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#define NXP_S32_EDMA0_TCD22_CLK 58U
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#define NXP_S32_EDMA0_TCD23_CLK 59U
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#define NXP_S32_EDMA0_TCD24_CLK 60U
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#define NXP_S32_EDMA0_TCD25_CLK 61U
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#define NXP_S32_EDMA0_TCD26_CLK 62U
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#define NXP_S32_EDMA0_TCD27_CLK 63U
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#define NXP_S32_EDMA0_TCD28_CLK 64U
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#define NXP_S32_EDMA0_TCD29_CLK 65U
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#define NXP_S32_EDMA0_TCD30_CLK 66U
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#define NXP_S32_EDMA0_TCD31_CLK 67U
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#define NXP_S32_EIM_CLK 68U
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#define NXP_S32_EMAC_RX_CLK 69U
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#define NXP_S32_EMAC0_RX_CLK 70U
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#define NXP_S32_EMAC_TS_CLK 71U
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#define NXP_S32_EMAC0_TS_CLK 72U
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#define NXP_S32_EMAC_TX_CLK 73U
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#define NXP_S32_EMAC0_TX_CLK 74U
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#define NXP_S32_EMIOS0_CLK 75U
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#define NXP_S32_EMIOS1_CLK 76U
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#define NXP_S32_EMIOS2_CLK 77U
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#define NXP_S32_ERM0_CLK 78U
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#define NXP_S32_FLEXCANA_CLK 79U
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#define NXP_S32_FLEXCAN0_CLK 80U
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#define NXP_S32_FLEXCAN1_CLK 81U
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#define NXP_S32_FLEXCAN2_CLK 82U
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#define NXP_S32_FLEXCANB_CLK 83U
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#define NXP_S32_FLEXCAN3_CLK 84U
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#define NXP_S32_FLEXCAN4_CLK 85U
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#define NXP_S32_FLEXCAN5_CLK 86U
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#define NXP_S32_FLEXIO0_CLK 87U
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#define NXP_S32_INTM_CLK 88U
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#define NXP_S32_LCU0_CLK 89U
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#define NXP_S32_LCU1_CLK 90U
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#define NXP_S32_LPI2C0_CLK 91U
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#define NXP_S32_LPI2C1_CLK 92U
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#define NXP_S32_LPSPI0_CLK 93U
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#define NXP_S32_LPSPI1_CLK 94U
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#define NXP_S32_LPSPI2_CLK 95U
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#define NXP_S32_LPSPI3_CLK 96U
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#define NXP_S32_LPSPI4_CLK 97U
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#define NXP_S32_LPSPI5_CLK 98U
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#define NXP_S32_LPUART0_CLK 99U
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#define NXP_S32_LPUART1_CLK 100U
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#define NXP_S32_LPUART2_CLK 101U
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#define NXP_S32_LPUART3_CLK 102U
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#define NXP_S32_LPUART4_CLK 103U
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#define NXP_S32_LPUART5_CLK 104U
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#define NXP_S32_LPUART6_CLK 105U
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#define NXP_S32_LPUART7_CLK 106U
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#define NXP_S32_LPUART8_CLK 107U
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#define NXP_S32_LPUART9_CLK 108U
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#define NXP_S32_LPUART10_CLK 109U
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#define NXP_S32_LPUART11_CLK 110U
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#define NXP_S32_LPUART12_CLK 111U
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#define NXP_S32_LPUART13_CLK 112U
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#define NXP_S32_LPUART14_CLK 113U
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#define NXP_S32_LPUART15_CLK 114U
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#define NXP_S32_MSCM_CLK 115U
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#define NXP_S32_MU2A_CLK 116U
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#define NXP_S32_MU2B_CLK 117U
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#define NXP_S32_PIT0_CLK 118U
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#define NXP_S32_PIT1_CLK 119U
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#define NXP_S32_PIT2_CLK 120U
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#define NXP_S32_QSPI0_CLK 121U
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#define NXP_S32_QSPI0_RAM_CLK 122U
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#define NXP_S32_QSPI0_TX_MEM_CLK 123U
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#define NXP_S32_QSPI_SFCK_CLK 124U
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#define NXP_S32_RTC_CLK 125U
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#define NXP_S32_RTC0_CLK 126U
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#define NXP_S32_SAI0_CLK 127U
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#define NXP_S32_SAI1_CLK 128U
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#define NXP_S32_SEMA42_CLK 129U
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#define NXP_S32_SIUL2_CLK 130U
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#define NXP_S32_STCU0_CLK 131U
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#define NXP_S32_STMA_CLK 132U
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#define NXP_S32_STM0_CLK 133U
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#define NXP_S32_STMB_CLK 134U
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#define NXP_S32_STM1_CLK 135U
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#define NXP_S32_SWT0_CLK 136U
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#define NXP_S32_TEMPSENSE_CLK 137U
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#define NXP_S32_TRACE_CLK 138U
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#define NXP_S32_TRGMUX0_CLK 139U
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#define NXP_S32_TSENSE0_CLK 140U
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#define NXP_S32_WKPU0_CLK 141U
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_ */
zephyr
dt-bindings
clock
nxp_s32k344_clock.h
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1.9.6