12#ifndef ZEPHYR_INCLUDE_SWDP_H_
13#define ZEPHYR_INCLUDE_SWDP_H_
22#define SWDP_REQUEST_APnDP BIT(0)
23#define SWDP_REQUEST_RnW BIT(1)
24#define SWDP_REQUEST_A2 BIT(2)
25#define SWDP_REQUEST_A3 BIT(3)
28#define SWDP_ACK_OK BIT(0)
29#define SWDP_ACK_WAIT BIT(1)
30#define SWDP_ACK_FAULT BIT(2)
33#define SWDP_TRANSFER_ERROR BIT(3)
36#define SWDP_SWCLK_PIN 0U
37#define SWDP_SWDIO_PIN 1U
38#define SWDP_nRESET_PIN 7U
state
Definition: parser_state.h:29
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
Runtime device structure (in ROM) per driver instance.
Definition: device.h:403
int(* swdp_input_sequence)(const struct device *dev, uint32_t count, uint8_t *data)
Read count bits from SWDIO into data LSB first.
Definition: swdp.h:65
int(* swdp_transfer)(const struct device *dev, uint8_t request, uint32_t *data, uint8_t idle_cycles, uint8_t *response)
Perform SWDP transfer and store response.
Definition: swdp.h:79
int(* swdp_output_sequence)(const struct device *dev, uint32_t count, const uint8_t *data)
Write count bits to SWDIO from data LSB first.
Definition: swdp.h:53
int(* swdp_configure)(const struct device *dev, uint8_t turnaround, bool data_phase)
Configure SWDP interface.
Definition: swdp.h:124
int(* swdp_port_on)(const struct device *dev)
Enable interface, set pins to default state.
Definition: swdp.h:136
int(* swdp_port_off)(const struct device *dev)
Disable interface, set pins to High-Z mode.
Definition: swdp.h:144
int(* swdp_set_clock)(const struct device *dev, uint32_t clock)
Set SWDP clock frequency.
Definition: swdp.h:114
int(* swdp_get_pins)(const struct device *dev, uint8_t *state)
Get SWCLK, SWDPIO, and nRESET pins state.
Definition: swdp.h:105
int(* swdp_set_pins)(const struct device *dev, uint8_t pins, uint8_t value)
Set SWCLK, SWDPIO, and nRESET pins state.
Definition: swdp.h:94