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microchip,xec-pcr

Vendor: Microchip Technology Inc.

Note

An implementation of a driver matching this compatible is available in drivers/clock_control/clock_control_mchp_xec.c.

Description

Microchip XEC Power Clock Reset and VBAT register (PCR)

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
core-clock-div	int	Divide 96 MHz PLL clock to produce Cortex-M4 core clock This property is required.
slow-clock-div	int	PWM and TACH clock domain divided down from 48 MHz AHB clock. The default value is 480 for 100 kHz.
pll-32k-src	int	32 KHz clock source for PLL This property is required.
periph-32k-src	int	32 KHz clock source for peripherals This property is required.
xtal-single-ended	boolean	Use single ended crystal connection to XTAL2 pin.
clk32kmon-period-min	int	32KHz clock monitor minimum valid 32KHz period in 48MHz units This property is required.
clk32kmon-period-max	int	32KHz clock monitor maximum valid 32KHz period in 48MHz units This property is required.
clk32kmon-duty-cycle-var-max	int	Maximum duty cycle variation. Difference in units of 48HMz between the measured 32KHz high and low pulse widths. This property is required.
clk32kmon-valid-min	int	Minimum number of consecutive 32KHz pulses that pass all monitor tests This property is required.
xtal-enable-delay-ms	int	Delay in milliseconds after crystal is enabled and clock monitor is started. This property is required. Default value: 300
pll-lock-timeout-ms	int	Timeout in milliseconds waiting for PLL to lock to new clock source. This property is required. Default value: 30
clkmon-bypass	boolean	Bypass clkmon check of crystal or XTAL2 single-ended clock.
internal-osc-disable	boolean	If the internal silicon 32KHz oscillator is not chosen as the source for PLL and Periheral devices then disable the internal 32KHz oscillator to save power.
#clock-cells	int	Number of items to expect in a Clock specifier This property is required. Constant value: 3
pinctrl-0	phandles	Pin configuration/s for the first state. Content is specific to the selected pin controller driver implementation.
pinctrl-1	phandles	Pin configuration/s for the second state. See pinctrl-0.
pinctrl-2	phandles	Pin configuration/s for the third state. See pinctrl-0.
pinctrl-3	phandles	Pin configuration/s for the fourth state. See pinctrl-0.
pinctrl-4	phandles	Pin configuration/s for the fifth state. See pinctrl-0.
pinctrl-names	string-array	Names for the provided states. The number of names needs to match the number of states.

Specifier cell names

• clock cells: regidx, bitpos, domain