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nordic,nrf-auxpll

Vendor: Nordic Semiconductor

Note

An implementation of a driver matching this compatible is available in drivers/clock_control/clock_control_nrf_auxpll.c.

Description

Nordic Auxiliary PLL (Phase Locked Loop)

The output frequency (f_out) of the auxiliary PLL is calculated as follows:

  f_out = ((R + A * 2^(-16)) * f_src) / B

where:

  - A: nordic,frequency
  - B: nordic,outdiv
  - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
  - f_src: Source frequency, given by clocks

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

nordic,ficrs

phandle-array

FICR entries, e.g. <&ficr OFFSET>. Available offsets (or FICR entries) are
available at <zephyr/dt-bindings/misc/nordic-nrf-ficr-*.h>.

This property is required.

nordic,frequency

int

Value used to set the fractional PLL divider ratio (can be set between
divider ratios 4 to 5). Valid values range from 0 to 65535.

This property is required.

nordic,out-div

int

PLL output divider.

Legal values: 1, 2, 3, 4, 6, 8, 12, 16

nordic,out-drive

int

Output buffer drive strength.

This property is required.

Legal values: 0, 1, 2, 3

nordic,current-tune

int

Constant current tune for the ring oscillator

This property is required.

nordic,sdm-disable

boolean

Disable sigma-delta modulator

nordic,dither-disable

boolean

Disable dither in sigma-delta modulator

nordic,range

string

PLL loop divider range

This property is required.

Legal values: 'low', 'mid', 'high', 'statichigh'

nordic,ficr-names

string-array

Names of each nordic,ficrs entry.