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st,stm32f1-pll-clock

Vendor: STMicroelectronics

Description

Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.

Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
as input clock.

Output clock frequency can be computed with the following formula:

  f(PLLCLK) = f(input clk) x PLLMUL  --> SYSCLK (System Clock)

The PLL output frequency must not exceed 72 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

mul

int

 
Main PLL multiplication factor for VCO
Valid range: 2 - 16

This property is required.

xtpre

boolean

 
Optional HSE divider for PLL entry

usbpre

boolean

 
Optional PLL output divisor to generate a 48MHz USB clock.
When set, PLL clock is not divided.
Otherwise, PLL output clock is divided by 1.5.