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st,stm32u0-pll-clock

Vendor: STMicroelectronics

Description

STM32U0 Main PLL node binding:

Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
  f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 122 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Division factor M of the PLL
input clock divider
Valid range: 1 - 8

This property is required.

mul-n

int

 
PLL frequency multiplication factor N
Valid range: 4 - 127

This property is required.

div-p

int

 
PLL VCO division factor P
Valid range: 2 - 32

div-q

int

 
PLL VCO division factor Q
Valid range: 2 - 8

div-r

int

 
PLL VCO division factor R
Valid range: 2 - 8

This property is required.