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snps,dwcxgmac-mdio

Vendor: Synopsys, Inc.

Note

An implementation of a driver matching this compatible is available in drivers/mdio/mdio_dwcxgmac.c.

Description

These nodes are “mdio” bus nodes.

Synopsys DWC XGMAC MDIO SMA Driver node

Properties

Properties not inherited from the base binding file.

Name

Type

Details

csr-clock-indx

int

MDIO csr reference clock speed
- 0: "100_150MHZ"
- 1: "150_250MHZ"
- 2: "250_300MHZ"
- 3: "300_350MHZ"
- 4: "350_400MHZ"
- 5: "450_500MHZ"

Default value: 1

clock-range-sel

boolean

When this field is true, it overrides the default
MDIO clock generation based on CSR clock.

resets

phandle-array

get reset line value

suppress-preamble

boolean

When present, the SMA suppresses the 32-bit preamble and transmits
MDIO frames with only 1 preamble bit. By default, the MDIO frame
always has 32 bits of preamble as defined in the IEEE 802.3 specs.

clock-frequency

int

Some MDIO controllers have the ability to configure the MDC frequency.
If present, this property may be used to specify the MDC frequency based
on what the PHYs connected to the mdio bus can support. Default of 2.5MHz
is the standard and should supported by all PHYs.

Default value: 2500000