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nxp,imx-csi

Vendor: NXP Semiconductors

Note

An implementation of a driver matching this compatible is available in drivers/video/video_mcux_csi.c.

Description

NXP MCUX CMOS sensor interface

Properties

Top level properties

These property descriptions apply to “nxp,imx-csi” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

Grandchild node properties

Name

Type

Details

remote-endpoint-label

string

Label of the 'remote-endpoint' subnode that interfaces with this endpoint.
This property is used as a 'work-around' to be able to declare the remote
endpoint and should be replaced by a "remote-endpoint" phandle property when
Zephyr devicetree supports circular dependency in the future.

This property is required.

bus-type

int

Data bus type.

Legal values: 1, 2, 3, 4, 5, 6

data-shift

int

On parallel data busses, if bus-width is used to specify the number of
data lines, data-shift can be used to specify which data lines are used,
e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.

hsync-active

int

Active state of the HSYNC signal

Legal values: 0, 1

vsync-active

int

Active state of the VSYNC signal.

Legal values: 0, 1

pclk-sample

int

Sample data on falling, rising or both edges of the pixel clock signal.

Legal values: 0, 1, 2

link-frequencies

array

Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
actual frequency of the bus, not bits per clock per lane value.

clock-lane

int

Physical clock lane index. Position of an entry determines the logical
lane number, while the value of an entry indicates physical lane, e.g. for
a MIPI CSI-2 bus we could have "clock-lane = <0>;", which places the
clock lane on hardware lane 0. This property is valid for serial busses
only (e.g. MIPI CSI-2).

data-lanes

array

An array of physical data lane indexes. Position of an entry determines
the logical lane number, while the value of an entry indicates physical
lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
assuming the clock lane is on hardware lane 0. If the hardware does not
support lane reordering, monotonically incremented values shall be used
from 0 or 1 onwards, depending on whether or not there is also a clock
lane. This property is valid for serial busses only (e.g. MIPI CSI-2).

bus-width

int

Number of data lines actively used, only valid for parallel busses.