nrf-pinctrl.h

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/*
 * Copyright (c) 2021 Nordic Semiconductor ASA
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
 
/*
 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
 * organized as follows:
 *
 * - 31..24: Pin function.
 * - 19-23:  Reserved.
 * - 18:     Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
 * - 17:     Clockpin enable.
 * - 16:     Pin inversion mode.
 * - 15:     Pin low power mode.
 * - 14..11: Pin output drive configuration.
 * - 10..9:  Pin pull configuration.
 * - 8..0:   Pin number (combination of port and pin).
 */
 
#define NRF_FUN_POS 24U
#define NRF_FUN_MSK 0xFFU
#define NRF_GPD_FAST_ACTIVE1_POS 18U
#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U
#define NRF_CLOCKPIN_ENABLE_POS 17U
#define NRF_CLOCKPIN_ENABLE_MSK 0x1U
#define NRF_INVERT_POS 16U
#define NRF_INVERT_MSK 0x1U
#define NRF_LP_POS 15U
#define NRF_LP_MSK 0x1U
#define NRF_DRIVE_POS 11U
#define NRF_DRIVE_MSK 0xFU
#define NRF_PULL_POS 9U
#define NRF_PULL_MSK 0x3U
#define NRF_PIN_POS 0U
#define NRF_PIN_MSK 0x1FFU
 
#define NRF_FUN_UART_TX 0U
#define NRF_FUN_UART_RX 1U
#define NRF_FUN_UART_RTS 2U
#define NRF_FUN_UART_CTS 3U
#define NRF_FUN_SPIM_SCK 4U
#define NRF_FUN_SPIM_MOSI 5U
#define NRF_FUN_SPIM_MISO 6U
#define NRF_FUN_SPIS_SCK 7U
#define NRF_FUN_SPIS_MOSI 8U
#define NRF_FUN_SPIS_MISO 9U
#define NRF_FUN_SPIS_CSN 10U
#define NRF_FUN_TWIM_SCL 11U
#define NRF_FUN_TWIM_SDA 12U
#define NRF_FUN_I2S_SCK_M 13U
#define NRF_FUN_I2S_SCK_S 14U
#define NRF_FUN_I2S_LRCK_M 15U
#define NRF_FUN_I2S_LRCK_S 16U
#define NRF_FUN_I2S_SDIN 17U
#define NRF_FUN_I2S_SDOUT 18U
#define NRF_FUN_I2S_MCK 19U
#define NRF_FUN_PDM_CLK 20U
#define NRF_FUN_PDM_DIN 21U
#define NRF_FUN_PWM_OUT0 22U
#define NRF_FUN_PWM_OUT1 23U
#define NRF_FUN_PWM_OUT2 24U
#define NRF_FUN_PWM_OUT3 25U
#define NRF_FUN_QDEC_A 26U
#define NRF_FUN_QDEC_B 27U
#define NRF_FUN_QDEC_LED 28U
#define NRF_FUN_QSPI_SCK 29U
#define NRF_FUN_QSPI_CSN 30U
#define NRF_FUN_QSPI_IO0 31U
#define NRF_FUN_QSPI_IO1 32U
#define NRF_FUN_QSPI_IO2 33U
#define NRF_FUN_QSPI_IO3 34U
#define NRF_FUN_EXMIF_CK 35U
#define NRF_FUN_EXMIF_DQ0 36U
#define NRF_FUN_EXMIF_DQ1 37U
#define NRF_FUN_EXMIF_DQ2 38U
#define NRF_FUN_EXMIF_DQ3 39U
#define NRF_FUN_EXMIF_DQ4 40U
#define NRF_FUN_EXMIF_DQ5 41U
#define NRF_FUN_EXMIF_DQ6 42U
#define NRF_FUN_EXMIF_DQ7 43U
#define NRF_FUN_EXMIF_CS0 44U
#define NRF_FUN_EXMIF_CS1 45U
#define NRF_FUN_CAN_TX 46U
#define NRF_FUN_CAN_RX 47U
 
#define NRF_DRIVE_S0S1 0U
#define NRF_DRIVE_H0S1 1U
#define NRF_DRIVE_S0H1 2U
#define NRF_DRIVE_H0H1 3U
#define NRF_DRIVE_D0S1 4U
#define NRF_DRIVE_D0H1 5U
#define NRF_DRIVE_S0D1 6U
#define NRF_DRIVE_H0D1 7U
#define NRF_DRIVE_E0E1 8U
 
#define NRF_PULL_NONE 0U
#define NRF_PULL_DOWN 1U
#define NRF_PULL_UP 3U
 
#define NRF_LP_DISABLE 0U
#define NRF_LP_ENABLE 1U
 
#define NRF_PIN_DISCONNECTED NRF_PIN_MSK
 
#define NRF_PSEL(fun, port, pin)                                                       \
        ((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) |                   \
         ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
 
#define NRF_PSEL_DISCONNECTED(fun)                                                     \
        (NRF_PIN_DISCONNECTED |                                                        \
         ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */