stm32f1-afio.h

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/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_STM32_AFIO_H_
#define ZEPHYR_STM32_AFIO_H_
 
#define STM32_REMAP_REG_MASK    0x1U
#define STM32_REMAP_REG_SHIFT   0U
#define STM32_REMAP_SHIFT_MASK  0x1FU
#define STM32_REMAP_SHIFT_SHIFT 1U
#define STM32_REMAP_MASK_MASK   0x3U
#define STM32_REMAP_MASK_SHIFT  6U
#define STM32_REMAP_VAL_MASK    0x3U
#define STM32_REMAP_VAL_SHIFT   8U
 
#define STM32_REMAP(val, mask, shift, reg)                                     \
        ((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) |           \
         (((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) |     \
         (((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) |        \
         (((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT))
 
 
/* Accessors for remap value */
 
#define STM32_REMAP_REG_GET(remap) \
        (((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)
 
#define STM32_REMAP_SHIFT_GET(remap) \
        (((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)
 
#define STM32_REMAP_MASK_GET(remap) \
        (((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)
 
#define STM32_REMAP_VAL_GET(remap) \
        (((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)
 
 
/* Remap values definitions, according to RM0008.pdf */
 
#define STM32_AFIO_MAPR         0U
#define STM32_AFIO_MAPR2        1U
 
#define NO_REMAP                0
 
#define SPI1_REMAP0             STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
#define SPI1_REMAP1             STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
 
#define I2C1_REMAP0             STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
#define I2C1_REMAP1             STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)
 
#define USART1_REMAP0           STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
#define USART1_REMAP1           STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)
 
#define USART2_REMAP0           STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
#define USART2_REMAP1           STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)
 
#define USART3_REMAP0           STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
#define USART3_REMAP1           STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)
#define USART3_REMAP2           STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)
 
#define TIM1_REMAP0             STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
#define TIM1_REMAP1             STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)
#define TIM1_REMAP2             STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)
 
#define TIM2_REMAP0             STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
#define TIM2_REMAP1             STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)
#define TIM2_REMAP2             STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)
#define TIM2_REMAP3             STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)
 
#define TIM3_REMAP0             STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)
#define TIM3_REMAP1             STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)
#define TIM3_REMAP2             STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)
#define TIM3_REMAP3             STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)
 
#define TIM4_REMAP0             STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)
#define TIM4_REMAP1             STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)
 
#define CAN_REMAP0              STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)
#define CAN_REMAP1              STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)
#define CAN_REMAP2              STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)
 
#define CAN1_REMAP0             CAN_REMAP0
#define CAN1_REMAP1             CAN_REMAP1
#define CAN1_REMAP2             CAN_REMAP2
 
#define ETH_REMAP0              STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)
#define ETH_REMAP1              STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)
 
#define CAN2_REMAP0             STM32_REMAP(0U, 0x1U, 22U, STM32_AFIO_MAPR)
#define CAN2_REMAP1             STM32_REMAP(1U, 0x1U, 22U, STM32_AFIO_MAPR)
 
#define SPI3_REMAP0             STM32_REMAP(0U, 0x1U, 28U, STM32_AFIO_MAPR)
#define SPI3_REMAP1             STM32_REMAP(1U, 0x1U, 28U, STM32_AFIO_MAPR)
 
#define I2S3_REMAP0             SPI3_REMAP0
#define I2S3_REMAP1             SPI3_REMAP1
 
#define TIM9_REMAP0             STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)
#define TIM9_REMAP1             STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)
 
#define TIM10_REMAP0            STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)
#define TIM10_REMAP1            STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)
 
#define TIM11_REMAP0            STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)
#define TIM11_REMAP1            STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)
 
#define TIM13_REMAP0            STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)
#define TIM13_REMAP1            STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)
 
#define TIM14_REMAP0            STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)
#define TIM14_REMAP1            STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)
 
#define TIM15_REMAP0            STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)
#define TIM15_REMAP1            STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)
 
#define TIM16_REMAP0            STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)
#define TIM16_REMAP1            STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)
 
#define TIM17_REMAP0            STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)
#define TIM17_REMAP1            STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
 
#endif  /* ZEPHYR_STM32_AFIO_H_ */