mpu.h

Go to the documentation of this file.

/*
 * Copyright (c) 2023 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#include <stdint.h>
 
#include <zephyr/toolchain.h>
#include <zephyr/sys/util_macro.h>
 
#include <xtensa/config/core-isa.h>
 
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
 
#define XTENSA_MPU_NUM_ENTRIES                  XCHAL_MPU_ENTRIES
 
#define XTENSA_MPU_ACCESS_P_NA_U_NA                     (0)
 
#define XTENSA_MPU_ACCESS_P_X_U_NA                      (2)
 
#define XTENSA_MPU_ACCESS_P_NA_U_X                      (3)
 
#define XTENSA_MPU_ACCESS_P_RO_U_NA                     (4)
 
#define XTENSA_MPU_ACCESS_P_RX_U_NA                     (5)
 
#define XTENSA_MPU_ACCESS_P_RW_U_NA                     (6)
 
#define XTENSA_MPU_ACCESS_P_RWX_U_NA                    (7)
 
#define XTENSA_MPU_ACCESS_P_WO_U_WO                     (8)
 
#define XTENSA_MPU_ACCESS_P_RW_U_RWX                    (9)
 
#define XTENSA_MPU_ACCESS_P_RW_U_RO                     (10)
 
#define XTENSA_MPU_ACCESS_P_RWX_U_RX                    (11)
 
#define XTENSA_MPU_ACCESS_P_RO_U_RO                     (12)
 
#define XTENSA_MPU_ACCESS_P_RX_U_RX                     (13)
 
#define XTENSA_MPU_ACCESS_P_RW_U_RW                     (14)
 
#define XTENSA_MPU_ACCESS_P_RWX_U_RWX                   (15)
 
struct xtensa_mpu_entry {
        union {
                uint32_t raw;
 
                struct {
                        uint32_t enable:1;
 
                        uint32_t lock:1;
 
                        uint32_t mbz:3;
 
                        uint32_t start_addr:27;
                } p;
        } as;
 
        union {
                uint32_t raw;
 
                struct {
                        uint32_t segment:5;
 
                        uint32_t mbz1:3;
 
                        uint32_t access_rights:4;
 
                        uint32_t memory_type:9;
 
                        uint32_t mbz2:11;
                } p;
        } at;
};
 
struct xtensa_mpu_map {
        struct xtensa_mpu_entry entries[XTENSA_MPU_NUM_ENTRIES];
};
 
typedef uint32_t k_mem_partition_attr_t;
 
static inline bool xtensa_mem_partition_is_executable(k_mem_partition_attr_t access_rights)
{
        bool is_exec;
 
        switch (access_rights) {
        case XTENSA_MPU_ACCESS_P_X_U_NA:
        case XTENSA_MPU_ACCESS_P_NA_U_X:
        case XTENSA_MPU_ACCESS_P_RX_U_NA:
        case XTENSA_MPU_ACCESS_P_RWX_U_NA:
        case XTENSA_MPU_ACCESS_P_RW_U_RWX:
        case XTENSA_MPU_ACCESS_P_RWX_U_RX:
        case XTENSA_MPU_ACCESS_P_RX_U_RX:
        case XTENSA_MPU_ACCESS_P_RWX_U_RWX:
                is_exec = true;
                break;
        default:
                is_exec = false;
                break;
        };
 
        return is_exec;
}
 
static inline bool xtensa_mem_partition_is_writable(k_mem_partition_attr_t access_rights)
{
        bool is_writable;
 
        switch (access_rights) {
        case XTENSA_MPU_ACCESS_P_RW_U_NA:
        case XTENSA_MPU_ACCESS_P_RWX_U_NA:
        case XTENSA_MPU_ACCESS_P_WO_U_WO:
        case XTENSA_MPU_ACCESS_P_RW_U_RWX:
        case XTENSA_MPU_ACCESS_P_RW_U_RO:
        case XTENSA_MPU_ACCESS_P_RWX_U_RX:
        case XTENSA_MPU_ACCESS_P_RW_U_RW:
        case XTENSA_MPU_ACCESS_P_RWX_U_RWX:
                is_writable = true;
                break;
        default:
                is_writable = false;
                break;
        };
 
        return is_writable;
}
 
#define K_MEM_PARTITION_IS_EXECUTABLE(access_rights) \
        (xtensa_mem_partition_is_executable(access_rights))
 
#define K_MEM_PARTITION_IS_WRITABLE(access_rights) \
        (xtensa_mem_partition_is_writable(access_rights))
 
/* Read-Write access permission attributes */
#define K_MEM_PARTITION_P_RW_U_RW \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_RW})
#define K_MEM_PARTITION_P_RW_U_NA \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_NA})
#define K_MEM_PARTITION_P_RO_U_RO \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_RO})
#define K_MEM_PARTITION_P_RO_U_NA \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_NA})
#define K_MEM_PARTITION_P_NA_U_NA \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_NA_U_NA})
 
/* Execution-allowed attributes */
#define K_MEM_PARTITION_P_RX_U_RX \
        ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RX_U_RX})
 
struct xtensa_mpu_range {
        const uintptr_t start;
 
        const uintptr_t end;
 
        const uint8_t access_rights:4;
 
        const uint16_t memory_type:9;
} __packed;
 
extern const struct xtensa_mpu_range xtensa_soc_mpu_ranges[];
 
extern const int xtensa_soc_mpu_ranges_num;
 
void xtensa_mpu_init(void);
 
#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H */