Line data Source code
1 1 : /*
2 : * Copyright (c) 2019 Synopsys.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : /**
8 : * @file
9 : * @brief ARCv2 ARC Connect driver
10 : *
11 : * ARCv2 ARC Connect driver interface. Included by arc/arch.h.
12 : */
13 :
14 : #ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_
15 : #define ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_
16 :
17 : #ifndef _ASMLANGUAGE
18 : #include <zephyr/types.h>
19 : #include <zephyr/arch/arc/v2/aux_regs.h>
20 :
21 : #ifdef __cplusplus
22 : extern "C" {
23 : #endif
24 :
25 : #define _ARC_V2_CONNECT_BCR 0x0d0
26 : #define _ARC_V2_CONNECT_IDU_BCR 0x0d5
27 : #define _ARC_V2_CONNECT_GFRC_BCR 0x0d6
28 : #define _ARC_V2_CONNECT_CMD 0x600
29 : #define _ARC_V2_CONNECT_WDATA 0x601
30 : #define _ARC_V2_CONNECT_READBACK 0x602
31 :
32 :
33 0 : #define ARC_CONNECT_CMD_CHECK_CORE_ID 0x0
34 :
35 0 : #define ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ 0x1
36 0 : #define ARC_CONNECT_CMD_INTRPT_GENERATE_ACK 0x2
37 0 : #define ARC_CONNECT_CMD_INTRPT_READ_STATUS 0x3
38 0 : #define ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE 0x4
39 :
40 0 : #define ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ 0x11
41 0 : #define ARC_CONNECT_CMD_SEMA_RELEASE 0x12
42 0 : #define ARC_CONNECT_CMD_SEMA_FORCE_RELEASE 0x13
43 :
44 0 : #define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR 0x21
45 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR 0x22
46 0 : #define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET 0x23
47 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET 0x24
48 0 : #define ARC_CONNECT_CMD_MSG_SRAM_WRITE 0x25
49 0 : #define ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC 0x26
50 0 : #define ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM 0x27
51 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ 0x28
52 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ_INC 0x29
53 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ_IMM 0x2a
54 0 : #define ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL 0x2b
55 0 : #define ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL 0x2c
56 :
57 0 : #define ARC_CONNECT_CMD_DEBUG_RESET 0x31
58 0 : #define ARC_CONNECT_CMD_DEBUG_HALT 0x32
59 0 : #define ARC_CONNECT_CMD_DEBUG_RUN 0x33
60 0 : #define ARC_CONNECT_CMD_DEBUG_SET_MASK 0x34
61 0 : #define ARC_CONNECT_CMD_DEBUG_READ_MASK 0x35
62 0 : #define ARC_CONNECT_CMD_DEBUG_SET_SELECT 0x36
63 0 : #define ARC_CONNECT_CMD_DEBUG_READ_SELECT 0x37
64 0 : #define ARC_CONNECT_CMD_DEBUG_READ_EN 0x38
65 0 : #define ARC_CONNECT_CMD_DEBUG_READ_CMD 0x39
66 0 : #define ARC_CONNECT_CMD_DEBUG_READ_CORE 0x3a
67 :
68 0 : #define ARC_CONNECT_CMD_DEBUG_MASK_SH 0x08 /* if a self-halt occurs, a global halt is triggered */
69 0 : #define ARC_CONNECT_CMD_DEBUG_MASK_BH 0x04 /* if a breakpoint caused halt occurs, a global halt is triggered */
70 0 : #define ARC_CONNECT_CMD_DEBUG_MASK_AH 0x02 /* if an actionpoint caused halt occurs, a global halt is triggered */
71 0 : #define ARC_CONNECT_CMD_DEBUG_MASK_H 0x01 /* whenever the core is halted, a global halt is triggered */
72 :
73 0 : #define ARC_CONNECT_CMD_GFRC_CLEAR 0x41
74 0 : #define ARC_CONNECT_CMD_GFRC_READ_LO 0x42
75 0 : #define ARC_CONNECT_CMD_GFRC_READ_HI 0x43
76 0 : #define ARC_CONNECT_CMD_GFRC_ENABLE 0x44
77 0 : #define ARC_CONNECT_CMD_GFRC_DISABLE 0x45
78 0 : #define ARC_CONNECT_CMD_GFRC_READ_DISABLE 0x46
79 0 : #define ARC_CONNECT_CMD_GFRC_SET_CORE 0x47
80 0 : #define ARC_CONNECT_CMD_GFRC_READ_CORE 0x48
81 0 : #define ARC_CONNECT_CMD_GFRC_READ_HALT 0x49
82 :
83 0 : #define ARC_CONNECT_CMD_PDM_SET_PM 0x81
84 0 : #define ARC_CONNECT_CMD_PDM_READ_PSTATUS 0x82
85 :
86 0 : #define ARC_CONNECT_CMD_PMU_SET_PUCNT 0x51
87 0 : #define ARC_CONNECT_CMD_PMU_READ_PUCNT 0x52
88 0 : #define ARC_CONNECT_CMD_PMU_SET_RSTCNT 0x53
89 0 : #define ARC_CONNECT_CMD_PMU_READ_RSTCNT 0x54
90 0 : #define ARC_CONNECT_CMD_PMU_SET_PDCNT 0x55
91 0 : #define ARC_CONNECT_CMD_PMU_READ_PDCNT 0x56
92 :
93 0 : #define ARC_CONNECT_CMD_IDU_ENABLE 0x71
94 0 : #define ARC_CONNECT_CMD_IDU_DISABLE 0x72
95 0 : #define ARC_CONNECT_CMD_IDU_READ_ENABLE 0x73
96 0 : #define ARC_CONNECT_CMD_IDU_SET_MODE 0x74
97 0 : #define ARC_CONNECT_CMD_IDU_READ_MODE 0x75
98 0 : #define ARC_CONNECT_CMD_IDU_SET_DEST 0x76
99 0 : #define ARC_CONNECT_CMD_IDU_READ_DEST 0x77
100 0 : #define ARC_CONNECT_CMD_IDU_GEN_CIRQ 0x78
101 0 : #define ARC_CONNECT_CMD_IDU_ACK_CIRQ 0x79
102 0 : #define ARC_CONNECT_CMD_IDU_CHECK_STATUS 0x7a
103 0 : #define ARC_CONNECT_CMD_IDU_CHECK_SOURCE 0x7b
104 0 : #define ARC_CONNECT_CMD_IDU_SET_MASK 0x7c
105 0 : #define ARC_CONNECT_CMD_IDU_READ_MASK 0x7d
106 0 : #define ARC_CONNECT_CMD_IDU_CHECK_FIRST 0x7e
107 :
108 : /* the start intno of common interrupt managed by IDU */
109 0 : #define ARC_CONNECT_IDU_IRQ_START 24
110 :
111 0 : #define ARC_CONNECT_INTRPT_TRIGGER_LEVEL 0
112 0 : #define ARC_CONNECT_INTRPT_TRIGGER_EDGE 1
113 :
114 :
115 0 : #define ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN 0
116 0 : #define ARC_CONNECT_DISTRI_MODE_FIRST_ACK 1
117 0 : #define ARC_CONNECT_DISTRI_ALL_DEST 2
118 :
119 0 : struct arc_connect_cmd {
120 : union {
121 : struct {
122 : #ifdef CONFIG_BIG_ENDIAN
123 : uint32_t pad:8, param:16, cmd:8;
124 : #else
125 0 : uint32_t cmd:8, param:16, pad:8;
126 : #endif
127 : };
128 0 : uint32_t val;
129 0 : };
130 : };
131 :
132 0 : struct arc_connect_bcr {
133 : union {
134 : struct {
135 : #ifdef CONFIG_BIG_ENDIAN
136 : uint32_t pad4:6, pw_dom:1, pad3:1,
137 : idu:1, pad2:1, num_cores:6,
138 : pad:1, gfrc:1, dbg:1, pw:1,
139 : msg:1, sem:1, ipi:1, slv:1,
140 : ver:8;
141 : #else
142 0 : uint32_t ver:8,
143 0 : slv:1, ipi:1, sem:1, msg:1,
144 0 : pw:1, dbg:1, gfrc:1, pad:1,
145 0 : num_cores:6, pad2:1, idu:1,
146 0 : pad3:1, pw_dom:1, pad4:6;
147 : #endif
148 : };
149 0 : uint32_t val;
150 0 : };
151 : };
152 :
153 0 : struct arc_connect_idu_bcr {
154 : union {
155 : struct {
156 : #ifdef CONFIG_BIG_ENDIAN
157 : uint32_t pad:21, cirqnum:3, ver:8;
158 : #else
159 0 : uint32_t ver:8, cirqnum:3, pad:21;
160 : #endif
161 : };
162 0 : uint32_t val;
163 0 : };
164 : };
165 :
166 : static inline void z_arc_connect_cmd(uint32_t cmd, uint32_t param)
167 : {
168 : struct arc_connect_cmd regval;
169 :
170 : regval.pad = 0;
171 : regval.cmd = cmd;
172 : regval.param = param;
173 :
174 : z_arc_v2_aux_reg_write(_ARC_V2_CONNECT_CMD, regval.val);
175 : }
176 :
177 : static inline void z_arc_connect_cmd_data(uint32_t cmd, uint32_t param,
178 : uint32_t data)
179 : {
180 : z_arc_v2_aux_reg_write(_ARC_V2_CONNECT_WDATA, data);
181 : z_arc_connect_cmd(cmd, param);
182 : }
183 :
184 : static inline uint32_t z_arc_connect_cmd_readback(void)
185 : {
186 : return z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_READBACK);
187 : }
188 :
189 :
190 : /* inter-core interrupt related functions */
191 : extern void z_arc_connect_ici_generate(uint32_t core_id);
192 : extern void z_arc_connect_ici_ack(uint32_t core_id);
193 : extern uint32_t z_arc_connect_ici_read_status(uint32_t core_id);
194 : extern uint32_t z_arc_connect_ici_check_src(void);
195 : extern void z_arc_connect_ici_clear(void);
196 :
197 : /* inter-core debug related functions */
198 : extern void z_arc_connect_debug_reset(uint32_t core_mask);
199 : extern void z_arc_connect_debug_halt(uint32_t core_mask);
200 : extern void z_arc_connect_debug_run(uint32_t core_mask);
201 : extern void z_arc_connect_debug_mask_set(uint32_t core_mask, uint32_t mask);
202 : extern uint32_t z_arc_connect_debug_mask_read(uint32_t core_mask);
203 : extern void z_arc_connect_debug_select_set(uint32_t core_mask);
204 : extern uint32_t z_arc_connect_debug_select_read(void);
205 : extern uint32_t z_arc_connect_debug_en_read(void);
206 : extern uint32_t z_arc_connect_debug_cmd_read(void);
207 : extern uint32_t z_arc_connect_debug_core_read(void);
208 :
209 : /* global free-running counter(gfrc) related functions */
210 : extern void z_arc_connect_gfrc_clear(void);
211 : extern uint64_t z_arc_connect_gfrc_read(void);
212 : extern void z_arc_connect_gfrc_enable(void);
213 : extern void z_arc_connect_gfrc_disable(void);
214 : extern void z_arc_connect_gfrc_core_set(uint32_t core_mask);
215 : extern uint32_t z_arc_connect_gfrc_halt_read(void);
216 : extern uint32_t z_arc_connect_gfrc_core_read(void);
217 :
218 : /* interrupt distribute unit related functions */
219 : extern void z_arc_connect_idu_enable(void);
220 : extern void z_arc_connect_idu_disable(void);
221 : extern uint32_t z_arc_connect_idu_read_enable(void);
222 : extern void z_arc_connect_idu_set_mode(uint32_t irq_num,
223 : uint16_t trigger_mode, uint16_t distri_mode);
224 : extern uint32_t z_arc_connect_idu_read_mode(uint32_t irq_num);
225 : extern void z_arc_connect_idu_set_dest(uint32_t irq_num, uint32_t core_mask);
226 : extern uint32_t z_arc_connect_idu_read_dest(uint32_t irq_num);
227 : extern void z_arc_connect_idu_gen_cirq(uint32_t irq_num);
228 : extern void z_arc_connect_idu_ack_cirq(uint32_t irq_num);
229 : extern uint32_t z_arc_connect_idu_check_status(uint32_t irq_num);
230 : extern uint32_t z_arc_connect_idu_check_source(uint32_t irq_num);
231 : extern void z_arc_connect_idu_set_mask(uint32_t irq_num, uint32_t mask);
232 : extern uint32_t z_arc_connect_idu_read_mask(uint32_t irq_num);
233 : extern uint32_t z_arc_connect_idu_check_first(uint32_t irq_num);
234 :
235 : #ifdef __cplusplus
236 : }
237 : #endif
238 :
239 : #endif /* _ASMLANGUAGE */
240 :
241 : #endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_ */
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