LCOV - code coverage report
Current view: top level - zephyr/arch/arm/cortex_a_r - exception.h Coverage Total Hit
Test: new.info Lines: 14.3 % 14 2
Test Date: 2025-09-05 20:47:19

            Line data    Source code
       1            1 : /*
       2              :  * Copyright (c) 2013-2014 Wind River Systems, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : /**
       8              :  * @file
       9              :  * @brief ARM AArch32 Cortex-A and Cortex-R public exception handling
      10              :  */
      11              : 
      12              : #ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_
      13              : #define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_
      14              : 
      15              : #ifdef _ASMLANGUAGE
      16              : GTEXT(z_arm_exc_exit);
      17              : #else
      18              : #include <zephyr/types.h>
      19              : 
      20              : #ifdef __cplusplus
      21              : extern "C" {
      22              : #endif
      23              : 
      24              : #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
      25              : 
      26              : /* Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls.
      27              :  *
      28              :  * Registers s0-s15 (d0-d7, q0-q3) do not have to be preserved (and can be used
      29              :  * for passing arguments or returning results in standard procedure-call variants).
      30              :  *
      31              :  * Registers d16-d31 (q8-q15), do not have to be preserved.
      32              :  */
      33              : struct __fpu_sf {
      34              :         uint32_t s[16]; /* s0~s15 (d0-d7) */
      35              : #ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
      36              :         uint64_t d[16]; /* d16~d31 */
      37              : #endif
      38              :         uint32_t fpscr;
      39              :         uint32_t undefined;
      40              : };
      41              : #endif
      42              : 
      43              : /* Additional register state that is not stacked by hardware on exception
      44              :  * entry.
      45              :  *
      46              :  * These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error().
      47              :  * When information for a member is unavailable, the field is set to zero.
      48              :  */
      49              : #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
      50              : struct __extra_esf_info {
      51              :         _callee_saved_t *callee;
      52              :         uint32_t msp;
      53              :         uint32_t exc_return;
      54              : };
      55              : #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
      56              : 
      57              : /* ARM GPRs are often designated by two different names */
      58            0 : #define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
      59              : 
      60            1 : struct arch_esf {
      61              : #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
      62              :         struct __extra_esf_info extra_info;
      63              : #endif
      64              : #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
      65            0 :         struct __fpu_sf fpu;
      66              : #endif
      67            0 :         struct __basic_sf {
      68            0 :                 sys_define_gpr_with_alias(a1, r0);
      69            0 :                 sys_define_gpr_with_alias(a2, r1);
      70            0 :                 sys_define_gpr_with_alias(a3, r2);
      71            0 :                 sys_define_gpr_with_alias(a4, r3);
      72            0 :                 sys_define_gpr_with_alias(ip, r12);
      73            0 :                 sys_define_gpr_with_alias(lr, r14);
      74            0 :                 sys_define_gpr_with_alias(pc, r15);
      75            0 :                 uint32_t xpsr;
      76            0 :         } basic;
      77              : };
      78              : 
      79              : extern uint32_t z_arm_coredump_fault_sp;
      80              : 
      81              : extern void z_arm_exc_exit(bool fatal);
      82              : 
      83              : #ifdef __cplusplus
      84              : }
      85              : #endif
      86              : 
      87              : #endif /* _ASMLANGUAGE */
      88              : 
      89              : #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_ */
        

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