LCOV - code coverage report
Current view: top level - zephyr/arch/arm/cortex_a_r - sys_io.h Coverage Total Hit
Test: new.info Lines: 0.0 % 8 0
Test Date: 2025-09-05 20:47:19

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2015, Wind River Systems, Inc.
       3              :  * Copyright (c) 2017, Oticon A/S
       4              :  *
       5              :  * SPDX-License-Identifier: Apache-2.0
       6              :  */
       7              : 
       8              : /* "Arch" bit manipulation functions in non-arch-specific C code (uses some
       9              :  * gcc builtins)
      10              :  */
      11              : 
      12              : #ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_SYS_IO_H_
      13              : #define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_SYS_IO_H_
      14              : 
      15              : #ifndef _ASMLANGUAGE
      16              : 
      17              : #include <zephyr/types.h>
      18              : #include <zephyr/sys/sys_io.h>
      19              : #include <zephyr/sys/barrier.h>
      20              : 
      21              : #ifdef __cplusplus
      22              : extern "C" {
      23              : #endif
      24              : 
      25              : /* Memory mapped registers I/O functions */
      26              : 
      27            0 : static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr)
      28              : {
      29              :         uint8_t val;
      30              : 
      31              :         __asm__ volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr));
      32              : 
      33              :         barrier_dmem_fence_full();
      34              :         return val;
      35              : }
      36              : 
      37            0 : static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr)
      38              : {
      39              :         barrier_dmem_fence_full();
      40              :         __asm__ volatile("strb %0, [%1]" : : "r" (data), "r" (addr));
      41              : }
      42              : 
      43            0 : static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
      44              : {
      45              :         uint16_t val;
      46              : 
      47              :         __asm__ volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
      48              : 
      49              :         barrier_dmem_fence_full();
      50              :         return val;
      51              : }
      52              : 
      53            0 : static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
      54              : {
      55              :         barrier_dmem_fence_full();
      56              :         __asm__ volatile("strh %0, [%1]" : : "r" (data), "r" (addr));
      57              : }
      58              : 
      59            0 : static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
      60              : {
      61              :         uint32_t val;
      62              : 
      63              :         __asm__ volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
      64              : 
      65              :         barrier_dmem_fence_full();
      66              :         return val;
      67              : }
      68              : 
      69            0 : static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
      70              : {
      71              :         barrier_dmem_fence_full();
      72              :         __asm__ volatile("str %0, [%1]" : : "r" (data), "r" (addr));
      73              : }
      74              : 
      75            0 : static ALWAYS_INLINE uint64_t sys_read64(mem_addr_t addr)
      76              : {
      77              :         uint64_t val;
      78              : 
      79              :         __asm__ volatile("ldrd %Q0, %R0, [%1]" : "=r" (val) : "r" (addr));
      80              : 
      81              :         barrier_dmem_fence_full();
      82              :         return val;
      83              : }
      84              : 
      85              : #ifdef __cplusplus
      86              : }
      87              : #endif
      88              : 
      89              : #endif /* _ASMLANGUAGE */
      90              : 
      91              : #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_SYS_IO_H_ */
        

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