Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2015, Wind River Systems, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef _CORTEX_M_CPU_H
       8              : #define _CORTEX_M_CPU_H
       9              : 
      10              : #ifdef _ASMLANGUAGE
      11              : 
      12              : #define _SCS_BASE_ADDR _PPB_INT_SCS
      13              : 
      14              : /* ICSR defines */
      15              : #define _SCS_ICSR           (_SCS_BASE_ADDR + 0xd04)
      16              : #define _SCS_ICSR_PENDSV    (1 << 28)
      17              : #define _SCS_ICSR_UNPENDSV  (1 << 27)
      18              : #define _SCS_ICSR_RETTOBASE (1 << 11)
      19              : 
      20              : #define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94)
      21              : 
      22              : /* CONTROL defines */
      23              : #define _CONTROL_FPCA_Msk (1 << 2)
      24              : 
      25              : /* EXC_RETURN defines */
      26              : #define _EXC_RETURN_SPSEL_Msk (1 << 2)
      27              : #define _EXC_RETURN_FTYPE_Msk (1 << 4)
      28              : 
      29              : /*
      30              :  * Cortex-M Exception Stack Frame Layouts
      31              :  *
      32              :  * When an exception is taken, the processor automatically pushes
      33              :  * registers to the current stack. The layout depends on whether
      34              :  * the FPU is active.
      35              :  */
      36              : 
      37              : /* Basic hardware-saved exception stack frame (no FPU context):
      38              :  *      R0-R3           (4 x 4B = 16B)
      39              :  *      R12             (4B)
      40              :  *      LR              (4B)
      41              :  *      Return address  (4B)
      42              :  *      RETPSR          (4B)
      43              :  *--------------------------
      44              :  *      Total: 32 bytes
      45              :  */
      46              : #define _EXC_HW_SAVED_BASIC_SF_SIZE             (32)
      47              : #define _EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET   (24)
      48              : #define _EXC_HW_SAVED_BASIC_SF_XPSR_OFFSET      (28)
      49              : 
      50              : /* Extended hardware saved stack frame consists of:
      51              :  *      R0-R3           (16B)
      52              :  *      R12             (4B)
      53              :  *      LR (R14)        (4B)
      54              :  *      Return address  (4B)
      55              :  *      RETPSR          (4B)
      56              :  *      S0-S15          (16 x 4B = 64B)
      57              :  *      FPSCR           (4B)
      58              :  *      Reserved        (4B)
      59              :  *--------------------------
      60              :  *      Total: 104 bytes
      61              :  */
      62              : #define _EXC_HW_SAVED_EXTENDED_SF_SIZE  (104)
      63              : 
      64              : #else
      65              : #include <stdint.h>
      66              : 
      67              : #ifdef __cplusplus
      68              : extern "C" {
      69              : #endif
      70              : 
      71              : /* CP10 Access Bits */
      72            0 : #define CPACR_CP10_Pos         20U
      73            0 : #define CPACR_CP10_Msk         (3UL << CPACR_CP10_Pos)
      74            0 : #define CPACR_CP10_NO_ACCESS   (0UL << CPACR_CP10_Pos)
      75            0 : #define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
      76            0 : #define CPACR_CP10_RESERVED    (2UL << CPACR_CP10_Pos)
      77            0 : #define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
      78              : 
      79              : /* CP11 Access Bits */
      80            0 : #define CPACR_CP11_Pos         22U
      81            0 : #define CPACR_CP11_Msk         (3UL << CPACR_CP11_Pos)
      82            0 : #define CPACR_CP11_NO_ACCESS   (0UL << CPACR_CP11_Pos)
      83            0 : #define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
      84            0 : #define CPACR_CP11_RESERVED    (2UL << CPACR_CP11_Pos)
      85            0 : #define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
      86              : 
      87              : #ifdef CONFIG_PM_S2RAM
      88              : 
      89              : struct __cpu_context {
      90              :         /* GPRs are saved onto the stack */
      91              :         uint32_t msp;
      92              :         uint32_t psp;
      93              :         uint32_t primask;
      94              :         uint32_t control;
      95              : 
      96              : #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
      97              :         /* Registers present only on ARMv7-M and ARMv8-M Mainline */
      98              :         uint32_t faultmask;
      99              :         uint32_t basepri;
     100              : #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
     101              : 
     102              : #if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
     103              :         /* Registers present only on certain ARMv8-M implementations */
     104              :         uint32_t msplim;
     105              :         uint32_t psplim;
     106              : #endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */
     107              : };
     108              : 
     109              : typedef struct __cpu_context _cpu_context_t;
     110              : 
     111              : #endif /* CONFIG_PM_S2RAM */
     112              : 
     113              : #ifdef __cplusplus
     114              : }
     115              : #endif
     116              : 
     117              : #endif /* _ASMLANGUAGE */
     118              : 
     119              : #endif /* _CORTEX_M_CPU_H */