Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2015, Wind River Systems, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef _CORTEX_M_CPU_H
       8              : #define _CORTEX_M_CPU_H
       9              : 
      10              : #ifdef _ASMLANGUAGE
      11              : 
      12              : #define _SCS_BASE_ADDR _PPB_INT_SCS
      13              : 
      14              : /* ICSR defines */
      15              : #define _SCS_ICSR           (_SCS_BASE_ADDR + 0xd04)
      16              : #define _SCS_ICSR_PENDSV    (1 << 28)
      17              : #define _SCS_ICSR_UNPENDSV  (1 << 27)
      18              : #define _SCS_ICSR_RETTOBASE (1 << 11)
      19              : 
      20              : #define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94)
      21              : 
      22              : /* CONTROL defines */
      23              : #define _CONTROL_FPCA_Msk (1 << 2)
      24              : 
      25              : /* EXC_RETURN defines */
      26              : #define _EXC_RETURN_SPSEL_Msk (1 << 2)
      27              : #define _EXC_RETURN_FTYPE_Msk (1 << 4)
      28              : 
      29              : #else
      30              : #include <stdint.h>
      31              : 
      32              : #ifdef __cplusplus
      33              : extern "C" {
      34              : #endif
      35              : 
      36              : /* CP10 Access Bits */
      37            0 : #define CPACR_CP10_Pos         20U
      38            0 : #define CPACR_CP10_Msk         (3UL << CPACR_CP10_Pos)
      39            0 : #define CPACR_CP10_NO_ACCESS   (0UL << CPACR_CP10_Pos)
      40            0 : #define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
      41            0 : #define CPACR_CP10_RESERVED    (2UL << CPACR_CP10_Pos)
      42            0 : #define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
      43              : 
      44              : /* CP11 Access Bits */
      45            0 : #define CPACR_CP11_Pos         22U
      46            0 : #define CPACR_CP11_Msk         (3UL << CPACR_CP11_Pos)
      47            0 : #define CPACR_CP11_NO_ACCESS   (0UL << CPACR_CP11_Pos)
      48            0 : #define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
      49            0 : #define CPACR_CP11_RESERVED    (2UL << CPACR_CP11_Pos)
      50            0 : #define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
      51              : 
      52              : #ifdef CONFIG_PM_S2RAM
      53              : 
      54              : struct __cpu_context {
      55              :         /* GPRs are saved onto the stack */
      56              :         uint32_t msp;
      57              :         uint32_t psp;
      58              :         uint32_t primask;
      59              :         uint32_t control;
      60              : 
      61              : #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
      62              :         /* Registers present only on ARMv7-M and ARMv8-M Mainline */
      63              :         uint32_t faultmask;
      64              :         uint32_t basepri;
      65              : #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
      66              : 
      67              : #if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
      68              :         /* Registers present only on certain ARMv8-M implementations */
      69              :         uint32_t msplim;
      70              :         uint32_t psplim;
      71              : #endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */
      72              : };
      73              : 
      74              : typedef struct __cpu_context _cpu_context_t;
      75              : 
      76              : #endif /* CONFIG_PM_S2RAM */
      77              : 
      78              : #ifdef __cplusplus
      79              : }
      80              : #endif
      81              : 
      82              : #endif /* _ASMLANGUAGE */
      83              : 
      84              : #endif /* _CORTEX_M_CPU_H */