Line data    Source code

       1            1 : /*
       2              :  * Copyright (c) 2014 Wind River Systems, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : /**
       8              :  * @file
       9              :  * @brief ARM CORTEX-M memory map
      10              :  *
      11              :  * This module contains definitions for the memory map of the CORTEX-M series of
      12              :  * processors.
      13              :  */
      14              : 
      15              : #ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_
      16              : #define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_
      17              : 
      18              : #include <zephyr/sys/util.h>
      19              : 
      20              : /* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
      21              : #define _CODE_BASE_ADDR 0x00000000
      22              : #define _CODE_END_ADDR  0x1FFFFFFF
      23              : 
      24              : /* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
      25              : #define _SRAM_BASE_ADDR           0x20000000
      26              : #define _SRAM_BIT_BAND_REGION     0x20000000
      27              : #define _SRAM_BIT_BAND_REGION_END 0x200FFFFF
      28              : #define _SRAM_BIT_BAND_ALIAS      0x22000000
      29              : #define _SRAM_BIT_BAND_ALIAS_END  0x23FFFFFF
      30              : #define _SRAM_END_ADDR            0x3FFFFFFF
      31              : 
      32              : /* 0x40000000 -> 0x5fffffff: Peripherals [0.5GB] */
      33              : #define _PERI_BASE_ADDR           0x40000000
      34              : #define _PERI_BIT_BAND_REGION     0x40000000
      35              : #define _PERI_BIT_BAND_REGION_END 0x400FFFFF
      36              : #define _PERI_BIT_BAND_ALIAS      0x42000000
      37              : #define _PERI_BIT_BAND_ALIAS_END  0x43FFFFFF
      38              : #define _PERI_END_ADDR            0x5FFFFFFF
      39              : 
      40              : /* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
      41              : #define _ERAM_BASE_ADDR 0x60000000
      42              : #define _ERAM_END_ADDR  0x9FFFFFFF
      43              : 
      44              : /* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
      45              : #define _EDEV_BASE_ADDR 0xA0000000
      46              : #define _EDEV_END_ADDR  0xDFFFFFFF
      47              : 
      48              : /* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
      49              : 
      50              : /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
      51              : /* 0xe0000000 -> 0xe003ffff: internal [256KB] */
      52              : #define _PPB_INT_BASE_ADDR 0xE0000000
      53              : #if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) ||                          \
      54              :         defined(CONFIG_CPU_CORTEX_M1)
      55              : #define _PPB_INT_RSVD_0 0xE0000000
      56              : #define _PPB_INT_DWT    0xE0001000
      57              : #define _PPB_INT_BPU    0xE0002000
      58              : #define _PPB_INT_RSVD_1 0xE0003000
      59              : #define _PPB_INT_SCS    0xE000E000
      60              : #define _PPB_INT_RSVD_2 0xE000F000
      61              : #elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) ||                            \
      62              :         defined(CONFIG_CPU_CORTEX_M7)
      63              : #define _PPB_INT_ITM    0xE0000000
      64              : #define _PPB_INT_DWT    0xE0001000
      65              : #define _PPB_INT_FPB    0xE0002000
      66              : #define _PPB_INT_RSVD_1 0xE0003000
      67              : #define _PPB_INT_SCS    0xE000E000
      68              : #define _PPB_INT_RSVD_2 0xE000F000
      69              : #elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) ||                          \
      70              :         defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85)
      71              : #define _PPB_INT_RSVD_0 0xE0000000
      72              : #define _PPB_INT_SCS    0xE000E000
      73              : #define _PPB_INT_SCB    0xE000ED00
      74              : #define _PPB_INT_RSVD_1 0xE002E000
      75              : #else
      76              : #error Unknown CPU
      77              : #endif
      78              : #define _PPB_INT_END_ADDR 0xE003FFFF
      79              : 
      80              : /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
      81              : /* 0xe0040000 -> 0xe00fffff: external [768K] */
      82              : #define _PPB_EXT_BASE_ADDR 0xE0040000
      83              : #if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) ||                          \
      84              :         defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
      85              : #elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
      86              : #define _PPB_EXT_TPIU      0xE0040000
      87              : #define _PPB_EXT_ETM       0xE0041000
      88              : #define _PPB_EXT_PPB       0xE0042000
      89              : #define _PPB_EXT_ROM_TABLE 0xE00FF000
      90              : #define _PPB_EXT_END_ADDR  0xE00FFFFF
      91              : #elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55) ||                          \
      92              :         defined(CONFIG_CPU_CORTEX_M85)
      93              : #undef _PPB_EXT_BASE_ADDR
      94              : #define _PPB_EXT_BASE_ADDR 0xE0044000
      95              : #define _PPB_EXT_ROM_TABLE 0xE00FF000
      96              : #define _PPB_EXT_END_ADDR  0xE00FFFFF
      97              : #elif defined(CONFIG_CPU_CORTEX_M7)
      98              : #define _PPB_EXT_BASE_ADDR      0xE0040000
      99              : #define _PPB_EXT_RSVD_TPIU      0xE0040000
     100              : #define _PPB_EXT_ETM            0xE0041000
     101              : #define _PPB_EXT_CTI            0xE0042000
     102              : #define _PPB_EXT_PPB            0xE0043000
     103              : #define _PPB_EXT_PROC_ROM_TABLE 0xE00FE000
     104              : #define _PPB_EXT_PPB_ROM_TABLE  0xE00FF000
     105              : #else
     106              : #error Unknown CPU
     107              : #endif
     108              : #define _PPB_EXT_END_ADDR 0xE00FFFFF
     109              : 
     110              : /* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB]  */
     111              : #define _VENDOR_BASE_ADDR 0xE0100000
     112              : #define _VENDOR_END_ADDR  0xFFFFFFFF
     113              : 
     114              : #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_ */