LCOV - code coverage report
Current view: top level - zephyr/arch/arm - gdbstub.h Coverage Total Hit
Test: new.info Lines: 10.5 % 19 2
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2023 Marek Vedral <vedrama5@fel.cvut.cz>
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_GDBSTUB_H_
       8              : #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_GDBSTUB_H_
       9              : 
      10              : #include <zephyr/arch/exception.h>
      11              : 
      12              : #ifndef _ASMLANGUAGE
      13              : 
      14            0 : #define DBGDSCR_MONITOR_MODE_EN 0x8000
      15              : 
      16            0 : #define SPSR_ISETSTATE_ARM     0x0
      17            0 : #define SPSR_ISETSTATE_JAZELLE 0x2
      18            0 : #define SPSR_J                 24
      19            0 : #define SPSR_T                 5
      20              : 
      21              : /* Debug Breakpoint Control Register constants */
      22            0 : #define DBGDBCR_MEANING_MASK          0x7
      23            0 : #define DBGDBCR_MEANING_SHIFT         20
      24            0 : #define DBGDBCR_MEANING_ADDR_MISMATCH 0x4
      25            0 : #define DBGDBCR_BYTE_ADDR_MASK        0xF
      26            0 : #define DBGDBCR_BYTE_ADDR_SHIFT       5
      27            0 : #define DBGDBCR_BRK_EN_MASK           0x1
      28              : 
      29              : /* Regno of the SPSR */
      30            0 : #define SPSR_REG_IDX    25
      31              : /* Minimal size of the packet - SPSR is the last, 42-nd byte, see packet_pos array */
      32            0 : #define GDB_READALL_PACKET_SIZE (42 * 8)
      33              : 
      34            0 : #define IFSR_DEBUG_EVENT 0x2
      35              : 
      36            0 : enum AARCH32_GDB_REG {
      37              :         R0 = 0,
      38              :         R1,
      39              :         R2,
      40              :         R3,
      41              :         /* READONLY registers (R4 - R13) except R12 */
      42              :         R4,
      43              :         R5,
      44              :         R6,
      45              :         R7,
      46              :         R8,
      47              :         R9,
      48              :         R10,
      49              :         R11,
      50              :         R12,
      51              :         /* Stack pointer - READONLY */
      52              :         R13,
      53              :         LR,
      54              :         PC,
      55              :         /* Saved program status register */
      56              :         SPSR,
      57              :         GDB_NUM_REGS
      58              : };
      59              : 
      60              : /* required structure */
      61            1 : struct gdb_ctx {
      62              :         /* cause of the exception */
      63            1 :         unsigned int exception;
      64            0 :         unsigned int registers[GDB_NUM_REGS];
      65              : };
      66              : 
      67              : void z_gdb_entry(struct arch_esf *esf, unsigned int exc_cause);
      68              : 
      69              : #endif
      70              : 
      71              : #endif
        

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