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1 0 : /*
2 : * Copyright (c) 2017 Linaro Limited.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 : #ifndef ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_H_
7 : #define ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_H_
8 :
9 : #if defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M3) || \
10 : defined(CONFIG_CPU_CORTEX_M4) || defined(CONFIG_CPU_CORTEX_M7) || defined(CONFIG_ARMV7_R)
11 : #include <zephyr/arch/arm/mpu/arm_mpu_v7m.h>
12 : #elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \
13 : defined(CONFIG_CPU_CORTEX_M52) || defined(CONFIG_CPU_CORTEX_M55) || \
14 : defined(CONFIG_CPU_CORTEX_M85) || defined(CONFIG_AARCH32_ARMV8_R)
15 : #include <zephyr/arch/arm/mpu/arm_mpu_v8.h>
16 : #else
17 : #error "Unsupported ARM CPU"
18 : #endif
19 :
20 : #if defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)
21 : /* PMSAv8 MPU */
22 : #define Z_ARM_CPU_HAS_PMSAV8_MPU 1
23 : #else
24 : /* PMSAv6 / PMSAv7 (MPU is identical) */
25 : #define Z_ARM_CPU_HAS_PMSAV8_MPU 0
26 : #endif
27 :
28 : #if defined(CONFIG_ARMV8_M_MAINLINE)
29 : #define Z_ARM_MPU_MAX_REGIONS 16U
30 : #else
31 : #define Z_ARM_MPU_MAX_REGIONS 8U
32 : #endif
33 :
34 :
35 : #ifndef _ASMLANGUAGE
36 : #include <stdint.h>
37 :
38 : /* Region definition data structure */
39 0 : struct arm_mpu_region {
40 : /* Region Base Address */
41 0 : uint32_t base;
42 : /* Region Name */
43 0 : const char *name;
44 : #if defined(CONFIG_CPU_AARCH32_CORTEX_R)
45 : /* Region Size */
46 : uint32_t size;
47 : #endif
48 : /* Region Attributes */
49 0 : arm_mpu_region_attr_t attr;
50 : };
51 :
52 : /* MPU configuration data structure */
53 0 : struct arm_mpu_config {
54 : /* Number of regions */
55 0 : uint32_t num_regions;
56 : /* Regions */
57 0 : const struct arm_mpu_region *mpu_regions;
58 : };
59 :
60 : #if defined(CONFIG_ARMV7_R)
61 : #define MPU_REGION_ENTRY(_name, _base, _size, _attr) \
62 : { \
63 : .name = _name, \
64 : .base = _base, \
65 : .size = _size, \
66 : .attr = _attr, \
67 : }
68 : #else
69 0 : #define MPU_REGION_ENTRY(_name, _base, _attr) \
70 : { \
71 : .name = _name, \
72 : .base = _base, \
73 : .attr = _attr, \
74 : }
75 : #endif
76 :
77 : /* Reference to the MPU configuration.
78 : *
79 : * This struct is defined and populated for each SoC (in the SoC definition),
80 : * and holds the build-time configuration information for the fixed MPU
81 : * regions enabled during kernel initialization. Dynamic MPU regions (e.g.
82 : * for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus,
83 : * not kept here.
84 : */
85 0 : extern const struct arm_mpu_config mpu_config;
86 :
87 : #if defined(CONFIG_CPU_CORTEX_M)
88 : /**
89 : * @brief MPU context structure to retain MPU register state across deep sleep.
90 : *
91 : * This structure holds the MPU region base and attribute registers,
92 : * as well as the MPU control register and a valid region count.
93 : *
94 : * The implemented architecture dictates which MPU registers exist:
95 : * - ARMv8-M has per-region RBAR+RLAR, and global MAIR0~1
96 : * - ARMv6/v7-M have per-region RBAR+RASR
97 : */
98 : struct z_mpu_context_retained {
99 : uint32_t rbar[Z_ARM_MPU_MAX_REGIONS];
100 : uint32_t rasr_rlar[Z_ARM_MPU_MAX_REGIONS];
101 : #if Z_ARM_CPU_HAS_PMSAV8_MPU
102 : uint32_t mair[2];
103 : #endif
104 : uint32_t ctrl;
105 : uint32_t num_valid_regions;
106 : };
107 :
108 : /**
109 : * @brief Save the current MPU configuration into the provided context struct.
110 : *
111 : * @param ctx Pointer to the MPU context structure to save into.
112 : */
113 : void z_arm_save_mpu_context(struct z_mpu_context_retained *ctx);
114 :
115 : /**
116 : * @brief Restore the MPU configuration from the provided context struct.
117 : *
118 : * @param ctx Pointer to the MPU context structure to restore from.
119 : */
120 : void z_arm_restore_mpu_context(const struct z_mpu_context_retained *ctx);
121 :
122 : #endif /* CONFIG_CPU_CORTEX_M */
123 : #endif /* _ASMLANGUAGE */
124 :
125 : #endif /* ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_H_ */
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