Line data Source code
1 0 : /*
2 : * Copyright (c) 2018 Linaro Limited.
3 : * Copyright (c) 2018 Nordic Semiconductor ASA.
4 : * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 : *
6 : * SPDX-License-Identifier: Apache-2.0
7 : */
8 :
9 : #ifndef _ASMLANGUAGE
10 :
11 : /* Convenience macros to represent the ARMv8-M-specific
12 : * configuration for memory access permission and
13 : * cache-ability attribution.
14 : */
15 : #if defined(CONFIG_AARCH32_ARMV8_R)
16 : #define MPU_IR_REGION_Msk (0xFFU)
17 : #define MPU_IR_REGION_Pos 8U
18 : /* MPU RBAR Register attribute msk Definitions */
19 : #define MPU_RBAR_BASE_Pos 6U
20 : #define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
21 : #define MPU_RBAR_SH_Pos 3U
22 : #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
23 : #define MPU_RBAR_AP_Pos 1U
24 : #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
25 : /* RBAR XN */
26 : #define MPU_RBAR_XN_Pos 0U
27 : #define MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos)
28 :
29 : /* MPU PLBAR Register Definitions */
30 : #define MPU_RLAR_LIMIT_Pos 6U
31 : #define MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
32 : #define MPU_RLAR_AttrIndx_Pos 1U
33 : #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
34 : #define MPU_RLAR_EN_Msk (0x1UL)
35 : #else
36 : #include <cmsis_core.h>
37 : #endif
38 :
39 : /* Privileged No Access, Unprivileged No Access */
40 : /*#define NO_ACCESS 0x0 */
41 : /*#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
42 : /* Privileged No Access, Unprivileged No Access */
43 : /*#define P_NA_U_NA 0x0 */
44 : /*#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
45 : /* Privileged Read Write, Unprivileged No Access */
46 0 : #define P_RW_U_NA 0x0
47 0 : #define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
48 : /* Privileged Read Write, Unprivileged Read Only */
49 : /*#define P_RW_U_RO 0x2 */
50 : /*#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)*/
51 : /* Privileged Read Write, Unprivileged Read Write */
52 0 : #define P_RW_U_RW 0x1
53 0 : #define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
54 : /* Privileged Read Write, Unprivileged Read Write */
55 0 : #define FULL_ACCESS 0x1
56 0 : #define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
57 : /* Privileged Read Only, Unprivileged No Access */
58 0 : #define P_RO_U_NA 0x2
59 0 : #define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
60 : /* Privileged Read Only, Unprivileged Read Only */
61 0 : #define P_RO_U_RO 0x3
62 0 : #define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
63 : /* Privileged Read Only, Unprivileged Read Only */
64 0 : #define RO 0x3
65 0 : #define RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
66 :
67 : /* Attribute flag for not-allowing execution (eXecute Never) */
68 0 : #define NOT_EXEC MPU_RBAR_XN_Msk
69 :
70 : /* To prevent execution of MPU region in privileged mode */
71 0 : #define PRIV_EXEC_NEVER (1)
72 :
73 : /* Attribute flags for share-ability */
74 0 : #define NON_SHAREABLE 0x0
75 0 : #define NON_SHAREABLE_Msk ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
76 0 : #define OUTER_SHAREABLE 0x2
77 0 : #define OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
78 0 : #define INNER_SHAREABLE 0x3
79 0 : #define INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
80 :
81 : /* Helper define to calculate the region limit address. */
82 0 : #define REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
83 :
84 : /* Attribute flags for cache-ability */
85 :
86 : /* Memory Attributes for Device Memory
87 : * 1.Gathering (G/nG)
88 : * Determines whether multiple accesses can be merged into a single
89 : * bus transaction.
90 : * nG: Number/size of accesses on the bus = number/size of accesses
91 : * in code.
92 : *
93 : * 2.Reordering (R/nR)
94 : * Determines whether accesses to the same device can be reordered.
95 : * nR: Accesses to the same IMPLEMENTATION DEFINED block size will
96 : * appear on the bus in program order.
97 : *
98 : * 3 Early Write Acknowledgment (E/nE)
99 : * Indicates to the memory system whether a buffer can send
100 : * acknowledgements.
101 : * nE: The response should come from the end slave, not buffering in
102 : * the interconnect.
103 : */
104 0 : #define DEVICE_nGnRnE 0x0U
105 0 : #define DEVICE_nGnRE 0x4U
106 0 : #define DEVICE_nGRE 0x8U
107 0 : #define DEVICE_GRE 0xCU
108 :
109 : /* Read/Write Allocation Configurations for Cacheable Memory */
110 0 : #define R_NON_W_NON 0x0 /* Do not allocate Read/Write */
111 0 : #define R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */
112 0 : #define R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */
113 0 : #define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */
114 :
115 : /* Memory Attributes for Normal Memory */
116 0 : #define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */
117 0 : #define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */
118 0 : #define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */
119 :
120 0 : #define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */
121 0 : #define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */
122 0 : #define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */
123 :
124 0 : #define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \
125 : ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | (NORMAL_I_WT_NT | R_ALLOC_W_NON))
126 :
127 0 : #define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \
128 : ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
129 :
130 0 : #define NORMAL_OUTER_INNER_NON_CACHEABLE \
131 : ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | (NORMAL_I_NON_C | R_NON_W_NON))
132 :
133 : /* Common cache-ability configuration for Flash, SRAM regions */
134 0 : #define MPU_CACHE_ATTRIBUTES_FLASH NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
135 : /* clang-format off */
136 0 : #define MPU_CACHE_ATTRIBUTES_SRAM \
137 : NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
138 : /* clang-format on */
139 0 : #define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE NORMAL_OUTER_INNER_NON_CACHEABLE
140 :
141 : /* Global MAIR configurations */
142 0 : #define MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH
143 0 : #define MPU_MAIR_INDEX_FLASH 0
144 0 : #define MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM
145 0 : #define MPU_MAIR_INDEX_SRAM 1
146 0 : #define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE
147 0 : #define MPU_MAIR_INDEX_SRAM_NOCACHE 2
148 0 : #define MPU_MAIR_ATTR_DEVICE DEVICE_nGnRnE
149 0 : #define MPU_MAIR_INDEX_DEVICE 3
150 : /* Flash region(s): Attribute-0
151 : * SRAM region(s): Attribute-1
152 : * SRAM no cache-able regions(s): Attribute-2
153 : * DEVICE no cache-able regions(s): Attribute-3
154 : */
155 0 : #define MPU_MAIR_ATTRS \
156 : ((MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) | \
157 : (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \
158 : (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) | \
159 : (MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)))
160 :
161 : /* Some helper defines for common regions.
162 : *
163 : * Note that the ARMv8-M/R MPU architecture requires that the
164 : * enabled MPU regions are non-overlapping. Therefore, it is
165 : * recommended to use these helper defines only for configuring
166 : * fixed MPU regions at build-time (i.e. regions that are not
167 : * expected to be re-programmed or re-adjusted at run-time so
168 : * that they do not overlap with other MPU regions).
169 : */
170 : #if defined(CONFIG_AARCH32_ARMV8_R)
171 :
172 : #define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
173 : { \
174 : .name = p_name, \
175 : .base = p_base, \
176 : .attr = p_attr(p_base + p_size), \
177 : }
178 :
179 : #define REGION_RAM_ATTR(limit) \
180 : { \
181 : .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
182 : .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
183 : .r_limit = limit - 1, /* Region Limit */ \
184 : }
185 :
186 : #define REGION_RAM_TEXT_ATTR(limit) \
187 : { \
188 : .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
189 : .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
190 : .r_limit = limit - 1, /* Region Limit */ \
191 : }
192 :
193 : #define REGION_RAM_RO_ATTR(limit) \
194 : { \
195 : .rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
196 : .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
197 : .r_limit = limit - 1, /* Region Limit */ \
198 : }
199 : #define REGION_RAM_NOCACHE_ATTR(limit) \
200 : { \
201 : .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
202 : .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
203 : .r_limit = limit - 1, /* Region Limit */ \
204 : }
205 : #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
206 : /* Note that the access permissions allow for un-privileged writes, contrary
207 : * to ARMv7-M where un-privileged code has Read-Only permissions.
208 : */
209 : #define REGION_FLASH_ATTR(limit) \
210 : { \
211 : .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
212 : .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
213 : .r_limit = limit - 1, /* Region Limit */ \
214 : }
215 : #else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
216 : #define REGION_FLASH_ATTR(limit) \
217 : { \
218 : .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
219 : .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
220 : .r_limit = limit - 1, /* Region Limit */ \
221 : }
222 : #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
223 :
224 : #define REGION_DEVICE_ATTR(limit) \
225 : { \
226 : .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
227 : .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
228 : .r_limit = limit - 1, /* Region Limit */ \
229 : }
230 : #else
231 :
232 0 : #define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
233 : { \
234 : .name = p_name, \
235 : .base = p_base, \
236 : .attr = p_attr(p_base, p_size), \
237 : }
238 :
239 : /* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
240 : * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
241 : * the SRAM region XN bit clear or the application code will not be executable.
242 : */
243 : /* clang-format off */
244 0 : #define REGION_RAM_ATTR(base, size) \
245 : { \
246 : .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk | \
247 : NON_SHAREABLE_Msk, /* AP, XN, SH */ \
248 : .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
249 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
250 : IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
251 : }
252 :
253 : #if defined(CONFIG_ARM_MPU_PXN)
254 : /* Use this attr to define an MPU region in RAM that has code intended to be executed in
255 : * un-privileged mode but not in privileged mode.
256 : */
257 : #define REGION_RAM_ATTR_PXN(base, size) \
258 : { \
259 : .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */ \
260 : .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
261 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
262 : .pxn = PRIV_EXEC_NEVER, \
263 : }
264 : #endif
265 :
266 0 : #define REGION_RAM_NOCACHE_ATTR(base, size) \
267 : { \
268 : .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
269 : .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
270 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
271 : IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
272 : }
273 :
274 : #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
275 : /* Note that the access permissions allow for un-privileged writes, contrary
276 : * to ARMv7-M where un-privileged code has Read-Only permissions.
277 : */
278 : #define REGION_FLASH_ATTR(base, size) \
279 : { \
280 : .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
281 : .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
282 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
283 : IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
284 : }
285 :
286 : #else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
287 0 : #define REGION_FLASH_ATTR(base, size) \
288 : { \
289 : .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
290 : .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
291 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
292 : IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
293 : }
294 :
295 : #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
296 :
297 0 : #define REGION_DEVICE_ATTR(base, size) \
298 : { \
299 : .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
300 : .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
301 : .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
302 : IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
303 : }
304 :
305 : /* clang-format on */
306 : #endif
307 :
308 : struct arm_mpu_region_attr {
309 : /* Attributes belonging to RBAR */
310 0 : uint8_t rbar: 5;
311 : /* MAIR index for attribute indirection */
312 0 : uint8_t mair_idx: 3;
313 : /* Region Limit Address value to be written to the RLAR register. */
314 0 : uint32_t r_limit;
315 : #ifdef CONFIG_ARM_MPU_PXN
316 : /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
317 : uint8_t pxn;
318 : #endif
319 : };
320 :
321 : typedef struct arm_mpu_region_attr arm_mpu_region_attr_t;
322 :
323 : /* Typedef for the k_mem_partition attribute */
324 : typedef struct {
325 0 : uint16_t rbar;
326 0 : uint16_t mair_idx;
327 : #ifdef CONFIG_ARM_MPU_PXN
328 : /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
329 : uint8_t pxn;
330 : #endif
331 : } k_mem_partition_attr_t;
332 :
333 : /* Kernel macros for memory attribution
334 : * (access permissions and cache-ability).
335 : *
336 : * The macros are to be stored in k_mem_partition_attr_t
337 : * objects. The format of a k_mem_partition_attr_t object
338 : * is as follows: field <rbar> contains a direct mapping
339 : * of the <XN> and <AP> bit-fields of the RBAR register;
340 : * field <mair_idx> contains a direct mapping of AttrIdx
341 : * bit-field, stored in RLAR register.
342 : */
343 :
344 : /* Read-Write access permission attributes */
345 0 : #define K_MEM_PARTITION_P_RW_U_RW \
346 : ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
347 0 : #define K_MEM_PARTITION_P_RW_U_NA \
348 : ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
349 0 : #define K_MEM_PARTITION_P_RO_U_RO \
350 : ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
351 0 : #define K_MEM_PARTITION_P_RO_U_NA \
352 : ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
353 :
354 : /* Execution-allowed attributes */
355 0 : #define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t){(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
356 0 : #define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
357 :
358 : #ifdef CONFIG_ARM_MPU_PXN
359 : #define K_MEM_PARTITION_P_R_U_RX \
360 : ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM, PRIV_EXEC_NEVER})
361 : #endif
362 :
363 : /*
364 : * @brief Evaluate Write-ability
365 : *
366 : * Evaluate whether the access permissions include write-ability.
367 : *
368 : * @param attr The k_mem_partition_attr_t object holding the
369 : * MPU attributes to be checked against write-ability.
370 : */
371 0 : #define K_MEM_PARTITION_IS_WRITABLE(attr) \
372 : ({ \
373 : int __is_writable__; \
374 : switch (attr.rbar & MPU_RBAR_AP_Msk) { \
375 : case P_RW_U_RW_Msk: \
376 : case P_RW_U_NA_Msk: \
377 : __is_writable__ = 1; \
378 : break; \
379 : default: \
380 : __is_writable__ = 0; \
381 : } \
382 : __is_writable__; \
383 : })
384 :
385 : /*
386 : * @brief Evaluate Execution allowance
387 : *
388 : * Evaluate whether the access permissions include execution.
389 : *
390 : * @param attr The k_mem_partition_attr_t object holding the
391 : * MPU attributes to be checked against execution
392 : * allowance.
393 : */
394 0 : #define K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rbar) & (NOT_EXEC)))
395 :
396 : /* Attributes for no-cache enabling (share-ability is selected by default) */
397 :
398 : /* Read-Write access permission attributes */
399 0 : #define K_MEM_PARTITION_P_RW_U_RW_NOCACHE \
400 : ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
401 : MPU_MAIR_INDEX_SRAM_NOCACHE})
402 0 : #define K_MEM_PARTITION_P_RW_U_NA_NOCACHE \
403 : ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
404 : MPU_MAIR_INDEX_SRAM_NOCACHE})
405 0 : #define K_MEM_PARTITION_P_RO_U_RO_NOCACHE \
406 : ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
407 : MPU_MAIR_INDEX_SRAM_NOCACHE})
408 0 : #define K_MEM_PARTITION_P_RO_U_NA_NOCACHE \
409 : ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
410 : MPU_MAIR_INDEX_SRAM_NOCACHE})
411 :
412 : /* Execution-allowed attributes */
413 0 : #define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE \
414 : ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), \
415 : MPU_MAIR_INDEX_SRAM_NOCACHE})
416 0 : #define K_MEM_PARTITION_P_RX_U_RX_NOCACHE \
417 : ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), \
418 : MPU_MAIR_INDEX_SRAM_NOCACHE})
419 :
420 : #endif /* _ASMLANGUAGE */
421 :
422 :
423 : /* Some compilers do not handle casts on pointers in constant expressions */
424 : #if defined(__IAR_SYSTEMS_ICC__)
425 : #define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
426 : BUILD_ASSERT( \
427 : (size > 0) && \
428 : ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
429 : "The start and size of the partition must align with the minimum MPU " \
430 : "region size.")
431 : #else
432 : #define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
433 : BUILD_ASSERT((size > 0) && \
434 : ((uint32_t)start % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
435 : ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
436 : "The start and size of the partition must align with the minimum MPU " \
437 : "region size.")
438 : #endif /* defined(__IAR_SYSTEMS_ICC__) */
|
