Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_ARCH_ARM64_TIMER_H_
       8             : #define ZEPHYR_INCLUDE_ARCH_ARM64_TIMER_H_
       9             : 
      10             : #ifndef _ASMLANGUAGE
      11             : 
      12             : #include <limits.h>
      13             : 
      14             : #include <zephyr/drivers/timer/arm_arch_timer.h>
      15             : #include <zephyr/types.h>
      16             : #include <limits.h>
      17             : 
      18             : #ifdef __cplusplus
      19             : extern "C" {
      20             : #endif
      21             : 
      22           0 : #define ARM_ARCH_TIMER_IRQ      ARM_TIMER_VIRTUAL_IRQ
      23           0 : #define ARM_ARCH_TIMER_PRIO     ARM_TIMER_VIRTUAL_PRIO
      24           0 : #define ARM_ARCH_TIMER_FLAGS    ARM_TIMER_VIRTUAL_FLAGS
      25             : 
      26           0 : static ALWAYS_INLINE void arm_arch_timer_init(void)
      27             : {
      28             : #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
      29             :         extern int z_clock_hw_cycles_per_sec;
      30             :         uint64_t cntfrq_el0 = read_cntfrq_el0();
      31             : 
      32             :         __ASSERT(cntfrq_el0 < INT_MAX, "cntfrq_el0 cannot fit in system 'int'");
      33             :         z_clock_hw_cycles_per_sec = (int) cntfrq_el0;
      34             : #endif
      35             : }
      36             : 
      37           0 : static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
      38             : {
      39             :         write_cntv_cval_el0(val);
      40             : }
      41             : 
      42           0 : static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
      43             : {
      44             :         uint64_t cntv_ctl;
      45             : 
      46             :         cntv_ctl = read_cntv_ctl_el0();
      47             : 
      48             :         if (enable) {
      49             :                 cntv_ctl |= CNTV_CTL_ENABLE_BIT;
      50             :         } else {
      51             :                 cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
      52             :         }
      53             : 
      54             :         write_cntv_ctl_el0(cntv_ctl);
      55             : }
      56             : 
      57           0 : static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
      58             : {
      59             :         uint64_t cntv_ctl;
      60             : 
      61             :         cntv_ctl = read_cntv_ctl_el0();
      62             : 
      63             :         if (mask) {
      64             :                 cntv_ctl |= CNTV_CTL_IMASK_BIT;
      65             :         } else {
      66             :                 cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
      67             :         }
      68             : 
      69             :         write_cntv_ctl_el0(cntv_ctl);
      70             : }
      71             : 
      72           0 : static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
      73             : {
      74             :         return read_cntvct_el0();
      75             : }
      76             : 
      77             : #ifdef __cplusplus
      78             : }
      79             : #endif
      80             : 
      81             : #endif /* _ASMLANGUAGE */
      82             : 
      83             : #endif /* ZEPHYR_INCLUDE_ARCH_ARM64_TIMER_H_ */