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1 0 : /* 2 : * Copyright (c) 2021 Intel Corporation 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : #ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_ 8 : #define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_ 9 : 10 : #ifndef _ASMLANGUAGE 11 : 12 : #include <zephyr/kernel_structs.h> 13 : #include "csr.h" 14 : #include "reg.h" 15 : 16 0 : static ALWAYS_INLINE uint32_t arch_proc_id(void) 17 : { 18 : return csr_read(mhartid) & ((uintptr_t)CONFIG_RISCV_HART_MASK); 19 : } 20 : 21 0 : static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void) 22 : { 23 : #if defined(CONFIG_SMP) || defined(CONFIG_USERSPACE) 24 : return (_cpu_t *)csr_read(mscratch); 25 : #else 26 : return &_kernel.cpus[0]; 27 : #endif 28 : } 29 : 30 : #ifdef CONFIG_RISCV_CURRENT_VIA_GP 31 : register struct k_thread *__arch_current_thread __asm__("gp"); 32 : 33 : #define arch_current_thread() __arch_current_thread 34 : #define arch_current_thread_set(thread) \ 35 : do { \ 36 : __arch_current_thread = _current_cpu->current = (thread); \ 37 : } while (0) 38 : #endif /* CONFIG_RISCV_CURRENT_VIA_GP */ 39 : 40 0 : static ALWAYS_INLINE unsigned int arch_num_cpus(void) 41 : { 42 : return CONFIG_MP_MAX_NUM_CPUS; 43 : } 44 : 45 : #endif /* !_ASMLANGUAGE */ 46 : #endif /* ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_ */