Line data    Source code

       1            1 : /*
       2              :  * Copyright (c) 2019 Intel Corp.
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  */
       5              : 
       6              : /**
       7              :  * @file
       8              :  * @brief Intel-64 specific kernel interface header
       9              :  *
      10              :  * This header contains the Intel-64 portion of the X86 specific kernel
      11              :  * interface (see include/zephyr/arch/x86/cpu.h).
      12              :  */
      13              : 
      14              : #ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
      15              : #define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
      16              : 
      17              : #include <zephyr/arch/exception.h>
      18              : #include <zephyr/kernel_structs.h>
      19              : #include <zephyr/arch/x86/intel64/exception.h>
      20              : #include <zephyr/arch/x86/intel64/thread.h>
      21              : #include <zephyr/arch/x86/thread_stack.h>
      22              : #if defined(CONFIG_PCIE) && !defined(_ASMLANGUAGE)
      23              : #include <zephyr/sys/iterable_sections.h>
      24              : #endif
      25              : 
      26              : #if CONFIG_ISR_STACK_SIZE != (CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH)
      27              : #error "Check ISR stack configuration (CONFIG_ISR_*)"
      28              : #endif
      29              : 
      30              : #if CONFIG_ISR_SUBSTACK_SIZE % ARCH_STACK_PTR_ALIGN
      31              : #error "CONFIG_ISR_SUBSTACK_SIZE must be a multiple of 16"
      32              : #endif
      33              : 
      34              : #ifndef _ASMLANGUAGE
      35              : 
      36            0 : static ALWAYS_INLINE void sys_write64(uint64_t data, mm_reg_t addr)
      37              : {
      38              :         __asm__ volatile("movq %0, %1"
      39              :                          :
      40              :                          : "r"(data), "m" (*(volatile uint64_t *)
      41              :                                            (uintptr_t) addr)
      42              :                          : "memory");
      43              : }
      44              : 
      45            0 : static ALWAYS_INLINE uint64_t sys_read64(mm_reg_t addr)
      46              : {
      47              :         uint64_t ret;
      48              : 
      49              :         __asm__ volatile("movq %1, %0"
      50              :                          : "=r"(ret)
      51              :                          : "m" (*(volatile uint64_t *)(uintptr_t) addr)
      52              :                          : "memory");
      53              : 
      54              :         return ret;
      55              : }
      56              : 
      57            0 : static ALWAYS_INLINE unsigned int arch_irq_lock(void)
      58              : {
      59              :         unsigned long key;
      60              : 
      61              :         __asm__ volatile ("pushfq; cli; popq %0" : "=g" (key) : : "memory");
      62              : 
      63              :         return (unsigned int) key;
      64              : }
      65              : 
      66            0 : #define ARCH_EXCEPT(reason_p) do { \
      67              :         __asm__ volatile( \
      68              :                 "movq %[reason], %%rax\n\t" \
      69              :                 "int $32\n\t" \
      70              :                 : \
      71              :                 : [reason] "i" (reason_p) \
      72              :                 : "memory"); \
      73              :         CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ \
      74              : } while (false)
      75              : 
      76              : #ifdef CONFIG_PCIE
      77              : #define X86_RESERVE_IRQ(irq_p, name) \
      78              :         static TYPE_SECTION_ITERABLE(uint8_t, name, irq_alloc, name) = irq_p
      79              : #else
      80            0 : #define X86_RESERVE_IRQ(irq_p, name)
      81              : #endif
      82              : 
      83              : #endif /* _ASMLANGUAGE */
      84              : 
      85              : /*
      86              :  * All Intel64 interrupts are dynamically connected.
      87              :  */
      88              : 
      89            0 : #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
      90              :         X86_RESERVE_IRQ(irq_p, _CONCAT(_irq_alloc_fixed, __COUNTER__)); \
      91              :         arch_irq_connect_dynamic(irq_p, priority_p,                     \
      92              :                                  (void (*)(const void *))isr_p,         \
      93              :                                  isr_param_p, flags_p)
      94              : 
      95              : #ifdef CONFIG_PCIE
      96              : 
      97              : #define ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p,                 \
      98              :                               isr_p, isr_param_p, flags_p)              \
      99              :         X86_RESERVE_IRQ(irq_p, _CONCAT(_irq_alloc_fixed, __COUNTER__)); \
     100              :         pcie_connect_dynamic_irq(bdf_p, irq_p, priority_p,              \
     101              :                                  (void (*)(const void *))isr_p,         \
     102              :                                  isr_param_p, flags_p)
     103              : 
     104              : #endif /* CONFIG_PCIE */
     105              : 
     106              : /*
     107              :  * Thread object needs to be 16-byte aligned.
     108              :  */
     109            0 : #define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT     16
     110              : 
     111              : #endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_ */