Line data Source code
1 0 : /*
2 : * Copyright (c) 2019 Intel Corp.
3 : * SPDX-License-Identifier: Apache-2.0
4 : */
5 :
6 : #ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
7 : #define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
8 :
9 : #ifndef _ASMLANGUAGE
10 : #include <zephyr/arch/x86/intel64/thread.h>
11 :
12 : #ifdef __cplusplus
13 : extern "C" {
14 : #endif
15 :
16 : /*
17 : * the exception stack frame
18 : */
19 :
20 : struct arch_esf {
21 : #ifdef CONFIG_EXCEPTION_DEBUG
22 : /* callee-saved */
23 : unsigned long rbx;
24 : unsigned long r12;
25 : unsigned long r13;
26 : unsigned long r14;
27 : unsigned long r15;
28 : #endif /* CONFIG_EXCEPTION_DEBUG */
29 0 : unsigned long rbp;
30 :
31 : /* Caller-saved regs */
32 0 : unsigned long rax;
33 0 : unsigned long rcx;
34 0 : unsigned long rdx;
35 0 : unsigned long rsi;
36 0 : unsigned long rdi;
37 0 : unsigned long r8;
38 0 : unsigned long r9;
39 0 : unsigned long r10;
40 : /* Must be aligned 16 bytes from the end of this struct due to
41 : * requirements of 'fxsave (%rsp)'
42 : */
43 0 : char fxsave[X86_FXSAVE_SIZE];
44 0 : unsigned long r11;
45 :
46 : /* Pushed by CPU or assembly stub */
47 0 : unsigned long vector;
48 0 : unsigned long code;
49 0 : unsigned long rip;
50 0 : unsigned long cs;
51 0 : unsigned long rflags;
52 0 : unsigned long rsp;
53 0 : unsigned long ss;
54 : };
55 :
56 0 : struct x86_ssf {
57 0 : unsigned long rip;
58 0 : unsigned long rflags;
59 0 : unsigned long r10;
60 0 : unsigned long r9;
61 0 : unsigned long r8;
62 0 : unsigned long rdx;
63 0 : unsigned long rsi;
64 0 : char fxsave[X86_FXSAVE_SIZE];
65 0 : unsigned long rdi;
66 0 : unsigned long rsp;
67 : };
68 :
69 : #ifdef __cplusplus
70 : }
71 : #endif
72 :
73 : #endif /* _ASMLANGUAGE */
74 :
75 : #endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_ */
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