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1 0 : /* 2 : * Copyright (c) 2020 Intel Corporation 3 : * SPDX-License-Identifier: Apache-2.0 4 : */ 5 : 6 : #ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H 7 : #define ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H 8 : 9 : #ifndef _ASMLANGUAGE 10 : 11 : /*************\ 12 : * Registers * 13 : \*************/ 14 : 15 0 : #define VTD_VER_REG 0x000 /* Version */ 16 0 : #define VTD_CAP_REG 0x008 /* Capability */ 17 0 : #define VTD_ECAP_REG 0x010 /* Extended Capability */ 18 0 : #define VTD_GCMD_REG 0x018 /* Global Command */ 19 0 : #define VTD_GSTS_REG 0x01C /* Global Status */ 20 0 : #define VTD_RTADDR_REG 0x020 /* Root Table Address */ 21 0 : #define VTD_CCMD_REG 0x028 /* Context Command */ 22 0 : #define VTD_FSTS_REG 0x034 /* Fault Status */ 23 0 : #define VTD_FECTL_REG 0x038 /* Fault Event Control */ 24 0 : #define VTD_FEDATA_REG 0x03C /* Fault Event Data */ 25 0 : #define VTD_FEADDR_REG 0x040 /* Fault Event Address */ 26 0 : #define VTD_FEUADDR_REG 0x044 /* Fault Event Upper Address */ 27 0 : #define VTD_AFLOG_REG 0x058 /* Advanced Fault Log */ 28 0 : #define VTD_PMEN_REG 0x064 /* Protected Memory Enable */ 29 0 : #define VTD_PLMBASE_REG 0x068 /* Protected Low Memory Base */ 30 0 : #define VTD_PLMLIMIT_REG 0x06C /* Protected Low Memory Limit */ 31 0 : #define VTD_PHMBASE_REG 0x070 /* Protected High Memory Base */ 32 0 : #define VTD_PHMLIMIT_REG 0x078 /* Protected High Memory Limit */ 33 0 : #define VTD_IQH_REG 0x080 /* Invalidation Queue Head */ 34 0 : #define VTD_IQT_REG 0x088 /* Invalidation Queue Tail */ 35 0 : #define VTD_IQA_REG 0x090 /* Invalidation Queue Address */ 36 0 : #define VTD_ICS_REG 0x09C /* Invalidation Completion Status */ 37 0 : #define VTD_IECTL_REG 0x0A0 /* Invalidation Completion Event Control */ 38 0 : #define VTD_IEDATA_REG 0x0A4 /* Invalidation Completion Event Data */ 39 0 : #define VTD_IEADDR_REG 0x0A8 /* Invalidation Completion Event Address */ 40 0 : #define VTD_IEUADDR_REG 0x0AC /* Invalidation Completion Event Upper Address */ 41 0 : #define VTD_IQERCD_REG 0x0B0 /* Invalidation Queue Error Record */ 42 0 : #define VTD_IRTA_REG 0x0B8 /* Interrupt Remapping Table Address */ 43 0 : #define VTD_PQH_REG 0x0C0 /* Page Request Queue Head */ 44 0 : #define VTD_PQT_REG 0x0C8 /* Page Request Queue Tail */ 45 0 : #define VTD_PQA_REG 0x0D0 /* Page Request Queue Address */ 46 0 : #define VTD_PRS_REG 0x0DC /* Page Request Status */ 47 0 : #define VTD_PECTL_REG 0x0E0 /* Page Request Event Control */ 48 0 : #define VTD_PEDATA_REG 0x0E4 /* Page Request Event Data */ 49 0 : #define VTD_PEADDR_REG 0x0E8 /* Page Request Event Address */ 50 0 : #define VTD_PEUADDR_REG 0x0EC /* Page Request Event Upper Address */ 51 0 : #define VTD_MTRRCAP_REG 0x100 /* MTRR Capability */ 52 0 : #define VTD_MTRRDEF_REG 0x108 /* MTRR Default Type */ 53 0 : #define VTD_MTRR_FIX64K_00000_REG 0x120 /* Fixed-range MTRR for 64K_00000 */ 54 0 : #define VTD_MTRR_FIX16K_80000_REG 0x128 /* Fixed-range MTRR for 16K_80000 */ 55 0 : #define VTD_MTRR_FIX16K_A0000_REG 0x130 /* Fixed-range MTRR for 16K_A0000 */ 56 0 : #define VTD_MTRR_FIX4K_C0000_REG 0x138 /* Fixed-range MTRR for 4K_C0000 */ 57 0 : #define VTD_MTRR_FIX4K_C8000_REG 0x140 /* Fixed-range MTRR for 4K_C8000 */ 58 0 : #define VTD_MTRR_FIX4K_D0000_REG 0x148 /* Fixed-range MTRR for 4K_D0000 */ 59 0 : #define VTD_MTRR_FIX4K_D8000_REG 0x150 /* Fixed-range MTRR for 4K_D8000 */ 60 0 : #define VTD_MTRR_FIX4K_E0000_REG 0x158 /* Fixed-range MTRR for 4K_E0000 */ 61 0 : #define VTD_MTRR_FIX4K_E8000_REG 0x160 /* Fixed-range MTRR for 4K_E8000 */ 62 0 : #define VTD_MTRR_FIX4K_F0000_REG 0x168 /* Fixed-range MTRR for 4K_F0000 */ 63 0 : #define VTD_MTRR_FIX4K_F8000_REG 0x170 /* Fixed-range MTRR for 4K_F8000 */ 64 0 : #define VTD_MTRR_PHYSBASE0_REG 0x180 /* Variable-range MTRR Base0 */ 65 0 : #define VTD_MTRR_PHYSMASK0_REG 0x188 /* Variable-range MTRR Mask0 */ 66 0 : #define VTD_MTRR_PHYSBASE1_REG 0x190 /* Variable-range MTRR Base1 */ 67 0 : #define VTD_MTRR_PHYSMASK1_REG 0x198 /* Variable-range MTRR Mask1 */ 68 0 : #define VTD_MTRR_PHYSBASE2_REG 0x1A0 /* Variable-range MTRR Base2 */ 69 0 : #define VTD_MTRR_PHYSMASK2_REG 0x1A8 /* Variable-range MTRR Mask2 */ 70 0 : #define VTD_MTRR_PHYSBASE3_REG 0x1B0 /* Variable-range MTRR Base3 */ 71 0 : #define VTD_MTRR_PHYSMASK3_REG 0x1B8 /* Variable-range MTRR Mask3 */ 72 0 : #define VTD_MTRR_PHYSBASE4_REG 0x1C0 /* Variable-range MTRR Base4 */ 73 0 : #define VTD_MTRR_PHYSMASK4_REG 0x1C8 /* Variable-range MTRR Mask4 */ 74 0 : #define VTD_MTRR_PHYSBASE5_REG 0x1D0 /* Variable-range MTRR Base5 */ 75 0 : #define VTD_MTRR_PHYSMASK5_REG 0x1D8 /* Variable-range MTRR Mask5 */ 76 0 : #define VTD_MTRR_PHYSBASE6_REG 0x1E0 /* Variable-range MTRR Base6 */ 77 0 : #define VTD_MTRR_PHYSMASK6_REG 0x1E8 /* Variable-range MTRR Mask6 */ 78 0 : #define VTD_MTRR_PHYSBASE7_REG 0x1F0 /* Variable-range MTRR Base7 */ 79 0 : #define VTD_MTRR_PHYSMASK7_REG 0x1F8 /* Variable-range MTRR Mask7 */ 80 0 : #define VTD_MTRR_PHYSBASE8_REG 0x200 /* Variable-range MTRR Base8 */ 81 0 : #define VTD_MTRR_PHYSMASK8_REG 0x208 /* Variable-range MTRR Mask8 */ 82 0 : #define VTD_MTRR_PHYSBASE9_REG 0x210 /* Variable-range MTRR Base9 */ 83 0 : #define VTD_MTRR_PHYSMASK9_REG 0x218 /* Variable-range MTRR Mask9 */ 84 0 : #define VTD_VCCAP_REG 0xE00 /* Virtual Command Capability */ 85 0 : #define VTD_VCMD 0xE10 /* Virtual Command */ 86 0 : #define VTD_VCRSP 0xE20 /* Virtual Command Response */ 87 : 88 : /* Capability Register details */ 89 0 : #define VTD_CAP_NFR_POS 40 90 0 : #define VTD_CAP_NFR_MASK ((uint64_t)0xFFUL << VTD_CAP_NFR_POS) 91 0 : #define VTD_CAP_NFR(cap) \ 92 : (((uint64_t)cap & VTD_CAP_NFR_MASK) >> VTD_CAP_NFR_POS) 93 : 94 0 : #define VTD_CAP_FRO_POS 24 95 0 : #define VTD_CAP_FRO_MASK ((uint64_t)0x3FFUL << VTD_CAP_FRO_POS) 96 0 : #define VTD_CAP_FRO(cap) \ 97 : (((uint64_t)cap & VTD_CAP_FRO_MASK) >> VTD_CAP_FRO_POS) 98 : 99 : /* Extended Capability Register details */ 100 0 : #define VTD_ECAP_C BIT(0) 101 : 102 : /* Global Command Register details */ 103 0 : #define VTD_GCMD_CFI 23 104 0 : #define VTD_GCMD_SIRTP 24 105 0 : #define VTD_GCMD_IRE 25 106 0 : #define VTD_GCMD_QIE 26 107 0 : #define VTD_GCMD_WBF 27 108 0 : #define VTD_GCMD_EAFL 28 109 0 : #define VTD_GCMD_SFL 29 110 0 : #define VTD_GCMD_SRTP 30 111 0 : #define VTD_GCMD_TE 31 112 : 113 : /* Global Status Register details */ 114 0 : #define VTD_GSTS_CFIS 23 115 0 : #define VTD_GSTS_SIRTPS 24 116 0 : #define VTD_GSTS_IRES 25 117 0 : #define VTD_GSTS_QIES 26 118 0 : #define VTD_GSTS_WBFS 27 119 0 : #define VTD_GSTS_EAFLS 28 120 0 : #define VTD_GSTS_SFLS 29 121 0 : #define VTD_GSTS_SRTPS 30 122 0 : #define VTD_GSTS_TES 31 123 : 124 : /* Interrupt Remapping Table Address Register details */ 125 0 : #define VTD_IRTA_SIZE_MASK 0x000000000000000FUL 126 0 : #define VTD_IRTA_EIME BIT(11) 127 : 128 0 : #define VTD_IRTA_REG_GEN_CONTENT(addr, size, mode) \ 129 : ((uint64_t)(addr) | (mode) | (size & VTD_IRTA_SIZE_MASK)) 130 : 131 : /* Fault event control register details */ 132 0 : #define VTD_FECTL_REG_IP 30 133 0 : #define VTD_FECTL_REG_IM 31 134 : 135 : /* Fault event status register details */ 136 0 : #define VTD_FSTS_PFO BIT(0) 137 0 : #define VTD_FSTS_PPF BIT(1) 138 0 : #define VTD_FSTS_AFO BIT(2) 139 0 : #define VTD_FSTS_APF BIT(3) 140 0 : #define VTD_FSTS_IQE BIT(4) 141 0 : #define VTD_FSTS_ICE BIT(5) 142 0 : #define VTD_FSTS_ITE BIT(6) 143 : 144 0 : #define VTD_FSTS_FRI_POS 8 145 0 : #define VTD_FSTS_FRI_MASK (0xF << VTD_FSTS_FRI_POS) 146 0 : #define VTD_FSTS_FRI(status) \ 147 : ((status & VTD_FSTS_FRI_MASK) >> VTD_FSTS_FRI_POS) 148 : 149 0 : #define VTD_FSTS_CLEAR_STATUS \ 150 : (VTD_FSTS_PFO | VTD_FSTS_AFO | VTD_FSTS_APF | \ 151 : VTD_FSTS_IQE | VTD_FSTS_ICE | VTD_FSTS_ITE) 152 : 153 0 : #define VTD_FSTS_CLEAR(status) \ 154 : (status & VTD_FSTS_CLEAR_STATUS) 155 : 156 : /* Fault recording register(s) details 157 : * Note: parts of the register are split into highest and lowest 64bits 158 : * so bit positions are depending on it and are not based on 128bits reg. 159 : */ 160 0 : #define VTD_FRCD_REG_SIZE 16 161 : 162 : /* Highest 64bits info */ 163 0 : #define VTD_FRCD_F BIT(63) 164 0 : #define VTD_FRCD_T BIT(62) 165 : 166 0 : #define VTD_FRCD_FR_POS 32 167 0 : #define VTD_FRCD_FR_MASK ((uint64_t)0xFF << VTD_FRCD_FR_POS) 168 0 : #define VTD_FRCD_FR(fault) \ 169 : ((uint8_t)((fault & VTD_FRCD_FR_MASK) >> VTD_FRCD_FR_POS)) 170 : 171 0 : #define VTD_FRCD_SID_MASK 0xFFFF 172 0 : #define VTD_FRCD_SID(fault) \ 173 : ((uint16_t)(fault & VTD_FRCD_SID_MASK)) 174 : 175 : /* Lowest 64bits info */ 176 0 : #define VTD_FRCD_FI_POS 12 177 0 : #define VTD_FRCD_FI_MASK ((uint64_t)0xFFFFFFFFFFFFF << VTD_FRCD_FI_POS) 178 0 : #define VTD_FRCD_FI(fault) \ 179 : ((fault & VTD_FRCD_FI_MASK) >> VTD_FRCD_FI_POS) 180 : 181 0 : #define VTD_FRCD_FI_IR_POS 48 182 0 : #define VTD_FRCD_FI_IR_MASK ((uint64_t)0xFFFF << VTD_FRCD_FI_IR_POS) 183 0 : #define VTD_FRCD_FI_IR(fault) \ 184 : ((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS) 185 : 186 : /* Invalidation Queue Address register details */ 187 0 : #define VTD_IQA_SIZE_MASK 0x7 188 0 : #define VTD_IQA_WIDTH_128_BIT 0 189 0 : #define VTD_IQA_WIDTH_256_BIT BIT(11) 190 0 : #define VTD_IQA_REG_GEN_CONTENT(addr, width, size) \ 191 : ((uint64_t)0 | (addr) | (width) | (size & VTD_IQA_SIZE_MASK)) 192 : 193 : /* Invalidation Queue Head register details */ 194 0 : #define VTD_IQH_QH_POS_128 4 195 0 : #define VTD_IQH_QH_MASK ((uint64_t)0xEF << VTD_IQH_QH_POS_128) 196 : 197 : /* Invalidation Queue Tail register details */ 198 0 : #define VTD_IQT_QT_POS_128 4 199 0 : #define VTD_IQT_QT_MASK ((uint64_t)0xEF << VTD_IQT_QT_POS_128) 200 : 201 : #endif /* _ASMLANGUAGE */ 202 : 203 : #endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H */
