Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2019 Intel Corp.
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  */
       5              : 
       6              : #ifndef ZEPHYR_INCLUDE_ARCH_X86_MSR_H_
       7              : #define ZEPHYR_INCLUDE_ARCH_X86_MSR_H_
       8              : 
       9              : #include <zephyr/toolchain.h>
      10              : 
      11              : /*
      12              :  * Model specific registers (MSR).  Access with z_x86_msr_read/write().
      13              :  */
      14              : 
      15            0 : #define X86_TIME_STAMP_COUNTER_MSR      0x00000010
      16              : 
      17            0 : #define X86_SPEC_CTRL_MSR               0x00000048
      18            0 : #define X86_SPEC_CTRL_MSR_IBRS          BIT(0)
      19            0 : #define X86_SPEC_CTRL_MSR_SSBD          BIT(2)
      20              : 
      21            0 : #define X86_APIC_BASE_MSR               0x0000001b
      22            0 : #define X86_APIC_BASE_MSR_X2APIC        BIT(10)
      23              : 
      24            0 : #define X86_MTRR_DEF_TYPE_MSR           0x000002ff
      25            0 : #define X86_MTRR_DEF_TYPE_MSR_ENABLE    BIT(11)
      26              : 
      27            0 : #define X86_X2APIC_BASE_MSR             0x00000800 /* .. thru 0x00000BFF */
      28              : 
      29            0 : #define X86_U_CET_MSR                   0x000006A0
      30              : 
      31            0 : #define X86_S_CET_MSR                   0x000006A2
      32            0 : #define X86_S_CET_MSR_SHSTK             BIT(0)
      33            0 : #define X86_S_CET_MSR_WR_SHSTK          BIT(1)
      34            0 : #define X86_S_CET_MSR_ENDBR             BIT(2)
      35            0 : #define X86_S_CET_MSR_NO_TRACK          BIT(4)
      36              : 
      37            0 : #define X86_S_CET_MSR_SHSTK_EN          (X86_S_CET_MSR_SHSTK | \
      38              :                                          X86_S_CET_MSR_WR_SHSTK)
      39              : 
      40            0 : #define X86_INTERRUPT_SSP_TABLE_MSR     0x00006A8
      41              : 
      42            0 : #define X86_EFER_MSR                    0xC0000080U
      43            0 : #define X86_EFER_MSR_SCE                BIT(0)
      44            0 : #define X86_EFER_MSR_LME                BIT(8)
      45            0 : #define X86_EFER_MSR_NXE                BIT(11)
      46              : 
      47              : /* STAR 31:0   Unused in long mode
      48              :  *      47:32  Kernel CS (SS = CS+8)
      49              :  *      63:48  User CS (SS = CS+8)
      50              :  */
      51            0 : #define X86_STAR_MSR                    0xC0000081U
      52              : 
      53              : /* Location for system call entry point */
      54            0 : #define X86_LSTAR_MSR                   0xC0000082U
      55              : 
      56              : /* Low 32 bits in this MSR are the SYSCALL mask applied to EFLAGS */
      57            0 : #define X86_FMASK_MSR                   0xC0000084U
      58              : 
      59            0 : #define X86_FS_BASE                     0xC0000100U
      60            0 : #define X86_GS_BASE                     0xC0000101U
      61            0 : #define X86_KERNEL_GS_BASE              0xC0000102U
      62              : 
      63              : #ifndef _ASMLANGUAGE
      64              : #ifdef __cplusplus
      65              : extern "C" {
      66              : #endif
      67              : 
      68              : /*
      69              :  * z_x86_msr_write() is shared between 32- and 64-bit implementations, but
      70              :  * due to ABI differences with long return values, z_x86_msr_read() is not.
      71              :  */
      72              : 
      73              : static inline void z_x86_msr_write(unsigned int msr, uint64_t data)
      74              : {
      75              :         uint32_t high = data >> 32;
      76              :         uint32_t low = data & 0xFFFFFFFFU;
      77              : 
      78              :         __asm__ volatile ("wrmsr" : : "c"(msr), "a"(low), "d"(high));
      79              : }
      80              : 
      81              : #ifdef CONFIG_X86_64
      82              : 
      83              : static inline uint64_t z_x86_msr_read(unsigned int msr)
      84              : {
      85              :         union {
      86              :                 struct {
      87              :                         uint32_t lo;
      88              :                         uint32_t hi;
      89              :                 };
      90              :                 uint64_t value;
      91              :         } rv;
      92              : 
      93              :         __asm__ volatile ("rdmsr" : "=a" (rv.lo), "=d" (rv.hi) : "c" (msr));
      94              : 
      95              :         return rv.value;
      96              : }
      97              : 
      98              : #else
      99              : 
     100              : static inline uint64_t z_x86_msr_read(unsigned int msr)
     101              : {
     102              :         uint64_t ret;
     103              : 
     104              :         __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
     105              : 
     106              :         return ret;
     107              : }
     108              : 
     109              : #endif
     110              : 
     111              : #ifdef __cplusplus
     112              : }
     113              : #endif
     114              : #endif /* _ASMLANGUAGE */
     115              : 
     116              : #endif /* ZEPHYR_INCLUDE_ARCH_X86_MSR_H_ */