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1 0 : /*
2 : * Copyright (c) 2021 Intel Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_H_
8 : #define ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_H_
9 :
10 : #include <stdint.h>
11 : #ifndef _ASMLANGUAGE
12 :
13 : #ifdef CONFIG_XTENSA_MPU
14 : #include <zephyr/arch/xtensa/mpu.h>
15 : #endif
16 :
17 : #ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING
18 : #include <xtensa/config/tie.h>
19 : #endif
20 :
21 : /* Xtensa doesn't use these structs, but Zephyr core requires they be
22 : * defined so they can be included in struct _thread_base. Dummy
23 : * field exists for sizeof compatibility with C++.
24 : */
25 :
26 : struct _callee_saved {
27 : char dummy;
28 : };
29 :
30 : typedef struct _callee_saved _callee_saved_t;
31 :
32 : struct _thread_arch {
33 : uint32_t last_cpu;
34 : #ifdef CONFIG_USERSPACE
35 :
36 : #ifdef CONFIG_XTENSA_MMU
37 : uint32_t *ptables;
38 : #endif
39 :
40 : #ifdef CONFIG_XTENSA_MPU
41 : /* Pointer to the memory domain's MPU map. */
42 : struct xtensa_mpu_map *mpu_map;
43 : #endif
44 :
45 : /* Initial privilege mode stack pointer when doing a system call.
46 : * Un-set for surpervisor threads.
47 : */
48 : uint8_t *psp;
49 :
50 : /* Stashed PS value used to restore PS when restoring from
51 : * context switching or returning from non-nested interrupts.
52 : */
53 : uint32_t return_ps;
54 : #endif
55 :
56 : #ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING
57 : /* A non-BSA region is required for lazy save/restore */
58 : uint8_t hifi_regs[XCHAL_CP1_SA_SIZE] __aligned(XCHAL_CP1_SA_ALIGN);
59 : #endif
60 : };
61 :
62 : typedef struct _thread_arch _thread_arch_t;
63 :
64 : #endif /* _ASMLANGUAGE */
65 :
66 : #endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_H_ */
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