Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2022 Intel Corporation
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_STACK_H_
       8             : #define ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_STACK_H_
       9             : 
      10             : #include <xtensa/config/core-isa.h>
      11             : #include <zephyr/toolchain.h>
      12             : #include <zephyr/sys/util.h>
      13             : 
      14             : #ifdef CONFIG_KERNEL_COHERENCE
      15             : #define ARCH_STACK_PTR_ALIGN XCHAL_DCACHE_LINESIZE
      16             : #else
      17           0 : #define ARCH_STACK_PTR_ALIGN 16
      18             : #endif
      19             : 
      20             : 
      21             : #ifdef CONFIG_USERSPACE
      22             : #ifdef CONFIG_XTENSA_MMU
      23             : #define XTENSA_STACK_BASE_ALIGN         CONFIG_MMU_PAGE_SIZE
      24             : #define XTENSA_STACK_SIZE_ALIGN         CONFIG_MMU_PAGE_SIZE
      25             : #endif
      26             : #ifdef CONFIG_XTENSA_MPU
      27             : #define XTENSA_STACK_BASE_ALIGN         XCHAL_MPU_ALIGN
      28             : #define XTENSA_STACK_SIZE_ALIGN         XCHAL_MPU_ALIGN
      29             : #endif
      30             : #else
      31             : #define XTENSA_STACK_BASE_ALIGN         ARCH_STACK_PTR_ALIGN
      32             : #define XTENSA_STACK_SIZE_ALIGN         ARCH_STACK_PTR_ALIGN
      33             : #endif
      34             : 
      35             : /*
      36             :  *
      37             :  * High memory addresses
      38             :  *
      39             :  * +-------------------+ <- thread.stack_info.start + thread.stack_info.size
      40             :  * |       TLS         |
      41             :  * +-------------------+ <- initial sp (computable with thread.stack_info.delta)
      42             :  * |                   |
      43             :  * |   Thread stack    |
      44             :  * |                   |
      45             :  * +-------------------+ <- thread.stack_info.start
      46             :  * | Privileged stack  | } CONFIG_MMU_PAGE_SIZE
      47             :  * +-------------------+ <- thread.stack_obj
      48             :  *
      49             :  * Low Memory addresses
      50             :  */
      51             : 
      52             : #ifndef _ASMLANGUAGE
      53             : 
      54             : /* thread stack */
      55           0 : struct xtensa_thread_stack_header {
      56             : #if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU)
      57             :         char privilege_stack[CONFIG_PRIVILEGED_STACK_SIZE];
      58             : #endif /* CONFIG_XTENSA_MPU */
      59             : } __packed __aligned(XTENSA_STACK_BASE_ALIGN);
      60             : 
      61             : #if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU)
      62             : #define ARCH_THREAD_STACK_RESERVED              \
      63             :         sizeof(struct xtensa_thread_stack_header)
      64             : #endif /* CONFIG_XTENSA_MMU || CONFIG_XTENSA_MPU */
      65             : 
      66           0 : #define ARCH_THREAD_STACK_OBJ_ALIGN(size)       XTENSA_STACK_BASE_ALIGN
      67           0 : #define ARCH_THREAD_STACK_SIZE_ADJUST(size)     \
      68             :         ROUND_UP((size), XTENSA_STACK_SIZE_ALIGN)
      69             : 
      70             : /* kernel stack */
      71           0 : #define ARCH_KERNEL_STACK_RESERVED              0
      72           0 : #define ARCH_KERNEL_STACK_OBJ_ALIGN             ARCH_STACK_PTR_ALIGN
      73             : 
      74             : #endif /* _ASMLANGUAGE */
      75             : 
      76             : #endif