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1 1 : /* 2 : * Copyright 2023 NXP 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : /** 8 : * @file 9 : * @brief Display definitions for MIPI devices 10 : */ 11 : 12 : #ifndef ZEPHYR_INCLUDE_DISPLAY_MIPI_DISPLAY_H_ 13 : #define ZEPHYR_INCLUDE_DISPLAY_MIPI_DISPLAY_H_ 14 : 15 : /** 16 : * @brief MIPI Display definitions 17 : * @defgroup mipi_interface MIPI Display interface 18 : * @ingroup io_interfaces 19 : * @{ 20 : */ 21 : 22 : 23 : #ifdef __cplusplus 24 : extern "C" { 25 : #endif 26 : 27 : /** 28 : * @name MIPI-DSI DCS (Display Command Set) 29 : * @{ 30 : */ 31 : 32 0 : #define MIPI_DCS_NOP 0x00U 33 0 : #define MIPI_DCS_SOFT_RESET 0x01U 34 0 : #define MIPI_DCS_GET_COMPRESSION_MODE 0x03U 35 0 : #define MIPI_DCS_GET_DISPLAY_ID 0x04U 36 0 : #define MIPI_DCS_GET_RED_CHANNEL 0x06U 37 0 : #define MIPI_DCS_GET_GREEN_CHANNEL 0x07U 38 0 : #define MIPI_DCS_GET_BLUE_CHANNEL 0x08U 39 0 : #define MIPI_DCS_GET_DISPLAY_STATUS 0x09U 40 0 : #define MIPI_DCS_GET_POWER_MODE 0x0AU 41 0 : #define MIPI_DCS_GET_ADDRESS_MODE 0x0BU 42 0 : #define MIPI_DCS_GET_PIXEL_FORMAT 0x0CU 43 0 : #define MIPI_DCS_GET_DISPLAY_MODE 0x0DU 44 0 : #define MIPI_DCS_GET_SIGNAL_MODE 0x0EU 45 0 : #define MIPI_DCS_GET_DIAGNOSTIC_RESULT 0x0FU 46 0 : #define MIPI_DCS_ENTER_SLEEP_MODE 0x10U 47 0 : #define MIPI_DCS_EXIT_SLEEP_MODE 0x11U 48 0 : #define MIPI_DCS_ENTER_PARTIAL_MODE 0x12U 49 0 : #define MIPI_DCS_ENTER_NORMAL_MODE 0x13U 50 0 : #define MIPI_DCS_EXIT_INVERT_MODE 0x20U 51 0 : #define MIPI_DCS_ENTER_INVERT_MODE 0x21U 52 0 : #define MIPI_DCS_SET_GAMMA_CURVE 0x26U 53 0 : #define MIPI_DCS_SET_DISPLAY_OFF 0x28U 54 0 : #define MIPI_DCS_SET_DISPLAY_ON 0x29U 55 0 : #define MIPI_DCS_SET_COLUMN_ADDRESS 0x2AU 56 0 : #define MIPI_DCS_SET_PAGE_ADDRESS 0x2BU 57 0 : #define MIPI_DCS_WRITE_MEMORY_START 0x2CU 58 0 : #define MIPI_DCS_WRITE_LUT 0x2DU 59 0 : #define MIPI_DCS_READ_MEMORY_START 0x2EU 60 0 : #define MIPI_DCS_SET_PARTIAL_ROWS 0x30U 61 0 : #define MIPI_DCS_SET_PARTIAL_COLUMNS 0x31U 62 0 : #define MIPI_DCS_SET_SCROLL_AREA 0x33U 63 0 : #define MIPI_DCS_SET_TEAR_OFF 0x34U 64 0 : #define MIPI_DCS_SET_TEAR_ON 0x35U 65 0 : #define MIPI_DCS_SET_ADDRESS_MODE 0x36U 66 0 : #define MIPI_DCS_SET_SCROLL_START 0x37U 67 0 : #define MIPI_DCS_EXIT_IDLE_MODE 0x38U 68 0 : #define MIPI_DCS_ENTER_IDLE_MODE 0x39U 69 0 : #define MIPI_DCS_SET_PIXEL_FORMAT 0x3AU 70 0 : #define MIPI_DCS_WRITE_MEMORY_CONTINUE 0x3CU 71 0 : #define MIPI_DCS_SET_3D_CONTROL 0x3DU 72 0 : #define MIPI_DCS_READ_MEMORY_CONTINUE 0x3EU 73 0 : #define MIPI_DCS_GET_3D_CONTROL 0x3FU 74 0 : #define MIPI_DCS_SET_VSYNC_TIMING 0x40U 75 0 : #define MIPI_DCS_SET_TEAR_SCANLINE 0x44U 76 0 : #define MIPI_DCS_GET_SCANLINE 0x45U 77 0 : #define MIPI_DCS_SET_DISPLAY_BRIGHTNESS 0x51U 78 0 : #define MIPI_DCS_GET_DISPLAY_BRIGHTNESS 0x52U 79 0 : #define MIPI_DCS_WRITE_CONTROL_DISPLAY 0x53U 80 0 : #define MIPI_DCS_GET_CONTROL_DISPLAY 0x54U 81 0 : #define MIPI_DCS_WRITE_POWER_SAVE 0x55U 82 0 : #define MIPI_DCS_GET_POWER_SAVE 0x56U 83 0 : #define MIPI_DCS_SET_CABC_MIN_BRIGHTNESS 0x5EU 84 0 : #define MIPI_DCS_GET_CABC_MIN_BRIGHTNESS 0x5FU 85 0 : #define MIPI_DCS_READ_DDB_START 0xA1U 86 0 : #define MIPI_DCS_READ_DDB_CONTINUE 0xA8U 87 : 88 0 : #define MIPI_DCS_PIXEL_FORMAT_24BIT 0x77 89 0 : #define MIPI_DCS_PIXEL_FORMAT_18BIT 0x66 90 0 : #define MIPI_DCS_PIXEL_FORMAT_16BIT 0x55 91 0 : #define MIPI_DCS_PIXEL_FORMAT_12BIT 0x33 92 0 : #define MIPI_DCS_PIXEL_FORMAT_8BIT 0x22 93 0 : #define MIPI_DCS_PIXEL_FORMAT_3BIT 0x11 94 : 95 : /** @} */ 96 : 97 : /** 98 : * @name MIPI-DSI Address mode register fields. 99 : * @{ 100 : */ 101 : 102 0 : #define MIPI_DCS_ADDRESS_MODE_MIRROR_Y BIT(7) 103 0 : #define MIPI_DCS_ADDRESS_MODE_MIRROR_X BIT(6) 104 0 : #define MIPI_DCS_ADDRESS_MODE_SWAP_XY BIT(5) 105 0 : #define MIPI_DCS_ADDRESS_MODE_REFRESH_BT BIT(4) 106 0 : #define MIPI_DCS_ADDRESS_MODE_BGR BIT(3) 107 0 : #define MIPI_DCS_ADDRESS_MODE_LATCH_RL BIT(2) 108 0 : #define MIPI_DCS_ADDRESS_MODE_FLIP_X BIT(1) 109 0 : #define MIPI_DCS_ADDRESS_MODE_FLIP_Y BIT(0) 110 : 111 : /** @} */ 112 : 113 : /** 114 : * @name MIPI-DSI Processor-to-Peripheral transaction types. 115 : * @{ 116 : */ 117 : 118 0 : #define MIPI_DSI_V_SYNC_START 0x01U 119 0 : #define MIPI_DSI_V_SYNC_END 0x11U 120 0 : #define MIPI_DSI_H_SYNC_START 0x21U 121 0 : #define MIPI_DSI_H_SYNC_END 0x31U 122 0 : #define MIPI_DSI_COLOR_MODE_OFF 0x02U 123 0 : #define MIPI_DSI_COLOR_MODE_ON 0x12U 124 0 : #define MIPI_DSI_SHUTDOWN_PERIPHERAL 0x22U 125 0 : #define MIPI_DSI_TURN_ON_PERIPHERAL 0x32U 126 0 : #define MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM 0x03U 127 0 : #define MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM 0x13U 128 0 : #define MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM 0x23U 129 0 : #define MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM 0x04U 130 0 : #define MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM 0x14U 131 0 : #define MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM 0x24U 132 0 : #define MIPI_DSI_DCS_SHORT_WRITE 0x05U 133 0 : #define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15U 134 0 : #define MIPI_DSI_DCS_READ 0x06U 135 0 : #define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37U 136 0 : #define MIPI_DSI_END_OF_TRANSMISSION 0x08U 137 0 : #define MIPI_DSI_NULL_PACKET 0x09U 138 0 : #define MIPI_DSI_BLANKING_PACKET 0x19U 139 0 : #define MIPI_DSI_GENERIC_LONG_WRITE 0x29U 140 0 : #define MIPI_DSI_DCS_LONG_WRITE 0x39U 141 0 : #define MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 0x0CU 142 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 0x1CU 143 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 0x2CU 144 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_30 0x0DU 145 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_36 0x1DU 146 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 0x3DU 147 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_16 0x0EU 148 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_18 0x1EU 149 0 : #define MIPI_DSI_PIXEL_STREAM_3BYTE_18 0x2EU 150 0 : #define MIPI_DSI_PACKED_PIXEL_STREAM_24 0x3EU 151 : 152 : /** @} */ 153 : 154 : 155 : #ifdef __cplusplus 156 : } 157 : #endif 158 : 159 : /** 160 : * @} 161 : */ 162 : 163 : #endif /* ZEPHYR_INCLUDE_DISPLAY_MIPI_DISPLAY_H_ */
