LCOV - code coverage report
Current view: top level - zephyr/drivers/clock_control - clock_agilex_ll.h Coverage Total Hit
Test: new.info Lines: 0.0 % 88 0
Test Date: 2025-09-05 20:47:19

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef CLOCKMANAGER_H
       8              : #define CLOCKMANAGER_H
       9              : 
      10              : #include <socfpga_handoff.h>
      11              : 
      12              : /* Clock Manager Registers */
      13            0 : #define CLKMGR_OFFSET                           0xffd10000
      14              : 
      15            0 : #define CLKMGR_CTRL                             0x0
      16            0 : #define CLKMGR_STAT                             0x4
      17            0 : #define CLKMGR_INTRCLR                          0x14
      18              : 
      19              : /* Main PLL Group */
      20            0 : #define CLKMGR_MAINPLL                          0xffd10024
      21            0 : #define CLKMGR_MAINPLL_EN                       0x0
      22            0 : #define CLKMGR_MAINPLL_BYPASS                   0xc
      23            0 : #define CLKMGR_MAINPLL_MPUCLK                   0x18
      24            0 : #define CLKMGR_MAINPLL_NOCCLK                   0x1c
      25            0 : #define CLKMGR_MAINPLL_NOCDIV                   0x20
      26            0 : #define CLKMGR_MAINPLL_PLLGLOB                  0x24
      27            0 : #define CLKMGR_MAINPLL_FDBCK                    0x28
      28            0 : #define CLKMGR_MAINPLL_MEM                      0x2c
      29            0 : #define CLKMGR_MAINPLL_MEMSTAT                  0x30
      30            0 : #define CLKMGR_MAINPLL_PLLC0                    0x34
      31            0 : #define CLKMGR_MAINPLL_PLLC1                    0x38
      32            0 : #define CLKMGR_MAINPLL_VCOCALIB                 0x3c
      33            0 : #define CLKMGR_MAINPLL_PLLC2                    0x40
      34            0 : #define CLKMGR_MAINPLL_PLLC3                    0x44
      35            0 : #define CLKMGR_MAINPLL_PLLM                     0x48
      36            0 : #define CLKMGR_MAINPLL_LOSTLOCK                 0x54
      37              : 
      38              : /* Peripheral PLL Group */
      39            0 : #define CLKMGR_PERPLL                           0xffd1007c
      40            0 : #define CLKMGR_PERPLL_EN                        0x0
      41            0 : #define CLKMGR_PERPLL_BYPASS                    0xc
      42            0 : #define CLKMGR_PERPLL_EMACCTL                   0x18
      43            0 : #define CLKMGR_PERPLL_GPIODIV                   0x1c
      44            0 : #define CLKMGR_PERPLL_PLLGLOB                   0x20
      45            0 : #define CLKMGR_PERPLL_FDBCK                     0x24
      46            0 : #define CLKMGR_PERPLL_MEM                       0x28
      47            0 : #define CLKMGR_PERPLL_MEMSTAT                   0x2c
      48            0 : #define CLKMGR_PERPLL_PLLC0                     0x30
      49            0 : #define CLKMGR_PERPLL_PLLC1                     0x34
      50            0 : #define CLKMGR_PERPLL_VCOCALIB                  0x38
      51            0 : #define CLKMGR_PERPLL_PLLC2                     0x3c
      52            0 : #define CLKMGR_PERPLL_PLLC3                     0x40
      53            0 : #define CLKMGR_PERPLL_PLLM                      0x44
      54            0 : #define CLKMGR_PERPLL_LOSTLOCK                  0x50
      55              : 
      56              : /* Altera Group */
      57            0 : #define CLKMGR_ALTERA                           0xffd100d0
      58            0 : #define CLKMGR_ALTERA_JTAG                      0x0
      59            0 : #define CLKMGR_ALTERA_EMACACTR                  0x4
      60            0 : #define CLKMGR_ALTERA_EMACBCTR                  0x8
      61            0 : #define CLKMGR_ALTERA_EMACPTPCTR                0xc
      62            0 : #define CLKMGR_ALTERA_GPIODBCTR                 0x10
      63            0 : #define CLKMGR_ALTERA_SDMMCCTR                  0x14
      64            0 : #define CLKMGR_ALTERA_S2FUSER0CTR               0x18
      65            0 : #define CLKMGR_ALTERA_S2FUSER1CTR               0x1c
      66            0 : #define CLKMGR_ALTERA_PSIREFCTR                 0x20
      67            0 : #define CLKMGR_ALTERA_EXTCNTRST                 0x24
      68              : 
      69              : /* Membus */
      70            0 : #define CLKMGR_MEM_REQ                          BIT(24)
      71            0 : #define CLKMGR_MEM_WR                           BIT(25)
      72            0 : #define CLKMGR_MEM_ERR                          BIT(26)
      73            0 : #define CLKMGR_MEM_WDAT_OFFSET                  16
      74            0 : #define CLKMGR_MEM_ADDR                         0x4027
      75            0 : #define CLKMGR_MEM_WDAT                         0x80
      76              : 
      77              : /* Clock Manager Macros */
      78            0 : #define CLKMGR_CTRL_BOOTMODE_SET_MSK            0x00000001
      79            0 : #define CLKMGR_STAT_BUSY_E_BUSY                 0x1
      80            0 : #define CLKMGR_STAT_BUSY(x)                     (((x) & 0x00000001) >> 0)
      81            0 : #define CLKMGR_STAT_MAINPLLLOCKED(x)            (((x) & 0x00000100) >> 8)
      82            0 : #define CLKMGR_STAT_PERPLLLOCKED(x)             (((x) & 0x00010000) >> 16)
      83            0 : #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK     0x00000004
      84            0 : #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK      0x00000008
      85            0 : #define CLKMGR_INTOSC_HZ                        460000000
      86              : 
      87              : /* Main PLL Macros */
      88            0 : #define CLKMGR_MAINPLL_EN_RESET                 0x000000ff
      89              : 
      90              : /* Peripheral PLL Macros */
      91            0 : #define CLKMGR_PERPLL_EN_RESET                  0x00000fff
      92            0 : #define CLKMGR_PERPLL_EN_SDMMCCLK               BIT(5)
      93            0 : #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x)  (((x) << 0) & 0x0000ffff)
      94              : 
      95              : /* Altera Macros */
      96            0 : #define CLKMGR_ALTERA_EXTCNTRST_RESET           0xff
      97              : 
      98              : /* Shared Macros */
      99            0 : #define CLKMGR_PSRC(x)                          (((x) & 0x00030000) >> 16)
     100            0 : #define CLKMGR_PSRC_MAIN                        0
     101            0 : #define CLKMGR_PSRC_PER                         1
     102              : 
     103            0 : #define CLKMGR_PLLGLOB_PSRC_EOSC1               0x0
     104            0 : #define CLKMGR_PLLGLOB_PSRC_INTOSC              0x1
     105            0 : #define CLKMGR_PLLGLOB_PSRC_F2S                 0x2
     106              : 
     107            0 : #define CLKMGR_PLLM_MDIV(x)                     ((x) & 0x000003ff)
     108            0 : #define CLKMGR_PLLGLOB_PD_SET_MSK               0x00000001
     109            0 : #define CLKMGR_PLLGLOB_RST_SET_MSK              0x00000002
     110              : 
     111            0 : #define CLKMGR_PLLGLOB_REFCLKDIV(x)             (((x) & 0x00003f00) >> 8)
     112            0 : #define CLKMGR_PLLGLOB_AREFCLKDIV(x)            (((x) & 0x00000f00) >> 8)
     113            0 : #define CLKMGR_PLLGLOB_DREFCLKDIV(x)            (((x) & 0x00003000) >> 12)
     114              : 
     115            0 : #define CLKMGR_VCOCALIB_HSCNT_SET(x)            (((x) << 0) & 0x000003ff)
     116            0 : #define CLKMGR_VCOCALIB_MSCNT_SET(x)            (((x) << 16) & 0x00ff0000)
     117              : 
     118            0 : #define CLKMGR_CLR_LOSTLOCK_BYPASS              0x20000000
     119              : 
     120            0 : void config_clkmgr_handoff(struct handoff *hoff_ptr);
     121            0 : uint32_t get_mpu_clk(void);
     122            0 : uint32_t get_wdt_clk(void);
     123            0 : uint32_t get_uart_clk(void);
     124            0 : uint32_t get_mmc_clk(void);
     125              : 
     126              : #endif
        

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