Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : /* Contains short functions relevant to timing and clocks common to all Bouffalolab platforms */
       8              : 
       9              : #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
      10              : #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
      11              : 
      12              : /* Common main clock mux (clock_bflb_set_root_clock) */
      13              : /* XCLK is RC32M, main clock is XCLK */
      14            0 : #define BFLB_MAIN_CLOCK_RC32M     0
      15              : /* XCLK is Crystal, main clock is XCLK */
      16            0 : #define BFLB_MAIN_CLOCK_XTAL      1
      17              : /* XCLK is RC32M, main clock is PLL */
      18            0 : #define BFLB_MAIN_CLOCK_PLL_RC32M 2
      19              : /* XCLK is Crystal, main clock is PLL */
      20            0 : #define BFLB_MAIN_CLOCK_PLL_XTAL  3
      21              : 
      22              : /* Function that busy waits for a few cycles */
      23            0 : static inline void clock_bflb_settle(void)
      24              : {
      25              :         __asm__ volatile (".rept 20 ; nop ; .endr");
      26              : }
      27              : 
      28            0 : static inline void clock_bflb_set_root_clock(uint32_t clock)
      29              : {
      30              :         uint32_t tmp;
      31              : 
      32              :         /* invalid value, fallback to internal 32M */
      33              :         if (clock > BFLB_MAIN_CLOCK_PLL_XTAL) {
      34              :                 clock = BFLB_MAIN_CLOCK_RC32M;
      35              :         }
      36              :         tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
      37              :         tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
      38              :         sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
      39              : 
      40              :         clock_bflb_settle();
      41              : }
      42              : 
      43            0 : static inline uint32_t clock_bflb_get_root_clock(void)
      44              : {
      45              :         uint32_t tmp;
      46              : 
      47              :         tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
      48              :         return ((tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS);
      49              : }
      50              : 
      51              : #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_ */