Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 : * an affiliate of Cypress Semiconductor Corporation
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 : #include <cy_sysclk.h>
9 : #include <cy_systick.h>
10 :
11 0 : #define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
12 :
13 : #if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
14 : /* Converts the group/div pair into a unique block number. */
15 0 : #define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
16 :
17 1 : #define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
18 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
19 : (gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider Group */ \
20 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
21 : (gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider Group */ \
22 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
23 : (gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \
24 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
25 : (gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */
26 : #else
27 : /* Converts the group/div pair into a unique block number. */
28 : #define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \
29 : (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div))
30 : #define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR)
31 : #define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \
32 : ((clock >> 2) - \
33 : (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR))
34 :
35 : #define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \
36 : IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \
37 : IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \
38 : IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \
39 : IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \
40 : IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \
41 : IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \
42 : IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \
43 : IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT)
44 : #endif
45 :
46 0 : enum ifx_cat1_clock_block {
47 : #if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
48 : /* The first four items are here for backwards compatibility with old clock APIs */
49 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< 8bit Peripheral Divider */
50 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
51 : CY_SYSCLK_DIV_16_BIT, /*!< 16bit Peripheral Divider */
52 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
53 : CY_SYSCLK_DIV_16_5_BIT, /*!< 16.5bit Peripheral Divider */
54 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
55 : CY_SYSCLK_DIV_24_5_BIT, /*!< 24.5bit Peripheral Divider */
56 :
57 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
58 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
59 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
60 : IFX_CAT1_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */
61 : IFX_CAT1_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */
62 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
63 : #if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
64 : IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
65 : #endif
66 :
67 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
68 : IFX_CAT1_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */
69 :
70 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
71 :
72 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
73 : #if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
74 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
75 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
76 : #else
77 : IFX_CAT1_CLOCK_BLOCK_PLL, /*!< Phase-Locked Loop Clock */
78 : #endif
79 :
80 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
81 : IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
82 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
83 :
84 : IFX_CAT1_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */
85 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
86 : IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< Timer Clock */
87 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
88 :
89 : IFX_CAT1_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM4 */
90 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock */
91 : IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */
92 :
93 : #elif defined(COMPONENT_CAT1B)
94 :
95 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
96 : CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
97 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
98 : CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
99 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
100 : CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
101 : */
102 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
103 : CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
104 : */
105 :
106 : /* The first four items are here for backwards compatibility with old clock APIs */
107 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
108 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
109 : #endif
110 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
111 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
112 : #endif
113 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
114 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
115 : #endif
116 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
117 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
118 : #endif
119 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
120 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
121 : #endif
122 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
123 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
124 : #endif
125 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
126 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
127 : #endif
128 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
129 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
130 : #endif
131 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
132 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
133 : #endif
134 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
135 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
136 : #endif
137 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
138 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
139 : #endif
140 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
141 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
142 : #endif
143 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
144 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
145 : #endif
146 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
147 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
148 : #endif
149 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
150 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
151 : #endif
152 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
153 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
154 : #endif
155 :
156 : IFX_CAT1_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */
157 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
158 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
159 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
160 : IFX_CAT1_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */
161 : IFX_CAT1_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */
162 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
163 : IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
164 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
165 : IFX_CAT1_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */
166 :
167 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
168 :
169 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
170 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
171 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
172 : IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */
173 :
174 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
175 : IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
176 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
177 :
178 : IFX_CAT1_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */
179 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
180 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
181 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
182 :
183 : #elif defined(COMPONENT_CAT1C)
184 :
185 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
186 : CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
187 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
188 : CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
189 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
190 : CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
191 : */
192 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
193 : CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
194 : */
195 :
196 : /* The first four items are here for backwards compatibility with old clock APIs */
197 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
198 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
199 : #endif
200 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
201 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
202 : #endif
203 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
204 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
205 : #endif
206 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
207 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
208 : #endif
209 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
210 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
211 : #endif
212 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
213 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
214 : #endif
215 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
216 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
217 : #endif
218 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
219 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
220 : #endif
221 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
222 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
223 : #endif
224 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
225 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
226 : #endif
227 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
228 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
229 : #endif
230 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
231 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
232 : #endif
233 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
234 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
235 : #endif
236 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
237 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
238 : #endif
239 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
240 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
241 : #endif
242 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
243 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
244 : #endif
245 :
246 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
247 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
248 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
249 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
250 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
251 :
252 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
253 :
254 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
255 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
256 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
257 :
258 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
259 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
260 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
261 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
262 :
263 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
264 : IFX_CAT1_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM7 */
265 : IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */
266 : IFX_CAT1_CLOCK_BLOCK_MEM, /*!< CLK MEM */
267 : IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< CLK Timer */
268 : #elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
269 :
270 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
271 : CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
272 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
273 : CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
274 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
275 : CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
276 : */
277 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
278 : CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
279 : */
280 :
281 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1)
282 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0),
283 : #endif
284 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2)
285 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1),
286 : #endif
287 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3)
288 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2),
289 : #endif
290 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4)
291 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3),
292 : #endif
293 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5)
294 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4),
295 : #endif
296 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6)
297 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5),
298 : #endif
299 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7)
300 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6),
301 : #endif
302 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8)
303 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7),
304 : #endif
305 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9)
306 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8),
307 : #endif
308 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10)
309 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9),
310 : #endif
311 : #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11)
312 : #warning "Unhandled PERI0 PCLK number"
313 : #endif
314 :
315 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1)
316 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0),
317 : #endif
318 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2)
319 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1),
320 : #endif
321 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3)
322 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2),
323 : #endif
324 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4)
325 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3),
326 : #endif
327 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5)
328 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4),
329 : #endif
330 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6)
331 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5),
332 : #endif
333 : #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7)
334 : #warning "Unhandled PERI1 PCLK number"
335 : #endif
336 :
337 : IFX_CAT1_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */
338 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
339 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
340 : IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
341 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
342 :
343 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
344 :
345 : IFX_CAT1_CLOCK_BLOCK_DPLL250, /*!< 250MHz Digital Phase-Locked Loop Clock */
346 : IFX_CAT1_CLOCK_BLOCK_DPLL500, /*!< 500MHz Digital Phase-Locked Loop Clock */
347 : IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */
348 :
349 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
350 : IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
351 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
352 :
353 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
354 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
355 :
356 : #endif
357 : };
358 :
359 0 : struct ifx_cat1_clock {
360 0 : enum ifx_cat1_clock_block block;
361 0 : uint8_t channel;
362 0 : bool reserved;
363 0 : const void *funcs;
364 : };
365 :
366 0 : struct ifx_cat1_resource_inst {
367 0 : uint8_t type; /* !< The resource block type */
368 0 : uint8_t block_num; /* !< The resource block index */
369 : /**
370 : * The channel number, if the resource type defines multiple channels
371 : * per block instance. Otherwise, 0
372 : */
373 1 : uint8_t channel_num;
374 : };
375 :
376 0 : int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
377 :
378 0 : en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num);
379 :
380 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
381 : const struct ifx_cat1_clock *_clock)
382 : {
383 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
384 : return Cy_SysClk_PeriPclkEnableDivider(
385 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
386 : _clock->channel);
387 : #else
388 : CY_UNUSED_PARAMETER(clk_dest);
389 : return Cy_SysClk_PeriphEnableDivider(
390 : IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
391 : #endif
392 : }
393 :
394 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
395 : const struct ifx_cat1_clock *_clock,
396 : uint32_t div)
397 : {
398 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
399 : return Cy_SysClk_PeriPclkSetDivider(
400 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
401 : _clock->channel, div);
402 : #else
403 : CY_UNUSED_PARAMETER(clk_dest);
404 : return Cy_SysClk_PeriphSetDivider(IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
405 : _clock->channel, div);
406 : #endif
407 : }
408 :
409 : static inline cy_rslt_t
410 0 : ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
411 : const struct ifx_cat1_clock *_clock, uint32_t div_int,
412 : uint32_t div_frac)
413 : {
414 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
415 : return Cy_SysClk_PeriPclkSetFracDivider(
416 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
417 : _clock->channel, div_int, div_frac);
418 : #else
419 : CY_UNUSED_PARAMETER(clk_dest);
420 : return Cy_SysClk_PeriphSetFracDivider(
421 : IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int,
422 : div_frac);
423 : #endif
424 : }
425 :
426 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
427 : const struct ifx_cat1_clock *_clock)
428 : {
429 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
430 : return Cy_SysClk_PeriPclkAssignDivider(
431 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
432 : _clock->channel);
433 : #else
434 : return Cy_SysClk_PeriphAssignDivider(
435 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
436 : _clock->channel);
437 : #endif
438 : }
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