Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 : * an affiliate of Cypress Semiconductor Corporation
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 : #include <cy_sysclk.h>
9 : #include <cy_systick.h>
10 :
11 0 : #define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
12 :
13 : /* Converts the group/div pair into a unique block number. */
14 0 : #define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
15 :
16 1 : #define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
17 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
18 : (gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider Group */ \
19 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
20 : (gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider Group */ \
21 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
22 : (gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \
23 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
24 : (gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */
25 :
26 0 : enum ifx_cat1_resource {
27 : IFX_CAT1_RSC_ADC, /*!< Analog to digital converter */
28 : IFX_CAT1_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */
29 : IFX_CAT1_RSC_BLESS, /*!< Bluetooth communications block */
30 : IFX_CAT1_RSC_CAN, /*!< CAN communication block */
31 : IFX_CAT1_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */
32 : IFX_CAT1_RSC_CLOCK, /*!< Clock */
33 : IFX_CAT1_RSC_CRYPTO, /*!< Crypto hardware accelerator */
34 : IFX_CAT1_RSC_DAC, /*!< Digital to analog converter */
35 : IFX_CAT1_RSC_DMA, /*!< DMA controller */
36 : IFX_CAT1_RSC_DW, /*!< Datawire DMA controller */
37 : IFX_CAT1_RSC_ETH, /*!< Ethernet communications block */
38 : IFX_CAT1_RSC_GPIO, /*!< General purpose I/O pin */
39 : IFX_CAT1_RSC_I2S, /*!< I2S communications block */
40 : IFX_CAT1_RSC_I3C, /*!< I3C communications block */
41 : IFX_CAT1_RSC_KEYSCAN, /*!< KeyScan block */
42 : IFX_CAT1_RSC_LCD, /*!< Segment LCD controller */
43 : IFX_CAT1_RSC_LIN, /*!< LIN communications block */
44 : IFX_CAT1_RSC_LPCOMP, /*!< Low power comparator */
45 : IFX_CAT1_RSC_LPTIMER, /*!< Low power timer */
46 : IFX_CAT1_RSC_OPAMP, /*!< Opamp */
47 : IFX_CAT1_RSC_PDM, /*!< PCM/PDM communications block */
48 : IFX_CAT1_RSC_PTC, /*!< Programmable Threshold comparator */
49 : IFX_CAT1_RSC_SMIF, /*!< Quad-SPI communications block */
50 : IFX_CAT1_RSC_RTC, /*!< Real time clock */
51 : IFX_CAT1_RSC_SCB, /*!< Serial Communications Block */
52 : IFX_CAT1_RSC_SDHC, /*!< SD Host Controller */
53 : IFX_CAT1_RSC_SDIODEV, /*!< SDIO Device Block */
54 : IFX_CAT1_RSC_TCPWM, /*!< Timer/Counter/PWM block */
55 : IFX_CAT1_RSC_TDM, /*!< TDM block */
56 : IFX_CAT1_RSC_UDB, /*!< UDB Array */
57 : IFX_CAT1_RSC_USB, /*!< USB communication block */
58 : IFX_CAT1_RSC_INVALID, /*!< Placeholder for invalid type */
59 : };
60 :
61 0 : enum ifx_cat1_clock_block {
62 : #if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
63 : /* The first four items are here for backwards compatibility with old clock APIs */
64 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< 8bit Peripheral Divider */
65 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
66 : CY_SYSCLK_DIV_16_BIT, /*!< 16bit Peripheral Divider */
67 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
68 : CY_SYSCLK_DIV_16_5_BIT, /*!< 16.5bit Peripheral Divider */
69 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
70 : CY_SYSCLK_DIV_24_5_BIT, /*!< 24.5bit Peripheral Divider */
71 :
72 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
73 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
74 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
75 : IFX_CAT1_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */
76 : IFX_CAT1_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */
77 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
78 : #if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
79 : IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
80 : #endif
81 :
82 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
83 : IFX_CAT1_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */
84 :
85 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
86 :
87 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
88 : #if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
89 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
90 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
91 : #else
92 : IFX_CAT1_CLOCK_BLOCK_PLL, /*!< Phase-Locked Loop Clock */
93 : #endif
94 :
95 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
96 : IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
97 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
98 :
99 : IFX_CAT1_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */
100 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
101 : IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< Timer Clock */
102 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
103 :
104 : IFX_CAT1_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM4 */
105 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock */
106 : IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */
107 :
108 : #elif defined(COMPONENT_CAT1B)
109 :
110 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
111 : CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
112 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
113 : CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
114 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
115 : CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
116 : */
117 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
118 : CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
119 : */
120 :
121 : /* The first four items are here for backwards compatibility with old clock APIs */
122 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
123 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
124 : #endif
125 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
126 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
127 : #endif
128 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
129 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
130 : #endif
131 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
132 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
133 : #endif
134 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
135 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
136 : #endif
137 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
138 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
139 : #endif
140 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
141 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
142 : #endif
143 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
144 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
145 : #endif
146 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
147 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
148 : #endif
149 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
150 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
151 : #endif
152 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
153 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
154 : #endif
155 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
156 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
157 : #endif
158 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
159 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
160 : #endif
161 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
162 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
163 : #endif
164 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
165 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
166 : #endif
167 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
168 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
169 : #endif
170 :
171 : IFX_CAT1_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */
172 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
173 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
174 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
175 : IFX_CAT1_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */
176 : IFX_CAT1_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */
177 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
178 : IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
179 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
180 : IFX_CAT1_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */
181 :
182 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
183 :
184 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
185 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
186 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
187 : IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */
188 :
189 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
190 : IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
191 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
192 :
193 : IFX_CAT1_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */
194 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
195 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
196 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
197 :
198 : #elif defined(COMPONENT_CAT1C)
199 :
200 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
201 : CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
202 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
203 : CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
204 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
205 : CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
206 : */
207 : IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
208 : CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
209 : */
210 :
211 : /* The first four items are here for backwards compatibility with old clock APIs */
212 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
213 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
214 : #endif
215 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
216 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
217 : #endif
218 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
219 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
220 : #endif
221 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
222 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
223 : #endif
224 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
225 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
226 : #endif
227 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
228 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
229 : #endif
230 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
231 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
232 : #endif
233 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
234 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
235 : #endif
236 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
237 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
238 : #endif
239 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
240 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
241 : #endif
242 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
243 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
244 : #endif
245 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
246 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
247 : #endif
248 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
249 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
250 : #endif
251 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
252 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
253 : #endif
254 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
255 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
256 : #endif
257 : #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
258 : IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
259 : #endif
260 :
261 : IFX_CAT1_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */
262 : IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
263 : IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
264 : IFX_CAT1_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */
265 : IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
266 :
267 : IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
268 :
269 : IFX_CAT1_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */
270 : IFX_CAT1_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */
271 : IFX_CAT1_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */
272 :
273 : IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
274 : IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
275 : IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
276 : IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */
277 :
278 : IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
279 : IFX_CAT1_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM7 */
280 : IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */
281 : IFX_CAT1_CLOCK_BLOCK_MEM, /*!< CLK MEM */
282 : IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< CLK Timer */
283 : #endif
284 : };
285 :
286 0 : struct ifx_cat1_clock {
287 0 : enum ifx_cat1_clock_block block;
288 0 : uint8_t channel;
289 0 : bool reserved;
290 0 : const void *funcs;
291 : };
292 :
293 0 : struct ifx_cat1_resource_inst {
294 0 : enum ifx_cat1_resource type; /* !< The resource block type */
295 0 : uint8_t block_num; /* !< The resource block index */
296 : /**
297 : * The channel number, if the resource type defines multiple channels
298 : * per block instance. Otherwise, 0
299 : */
300 1 : uint8_t channel_num;
301 : };
302 :
303 0 : int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
304 :
305 0 : en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num);
306 :
307 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
308 : const struct ifx_cat1_clock *_clock)
309 : {
310 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
311 : return Cy_SysClk_PeriPclkEnableDivider(
312 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
313 : _clock->channel);
314 : #else
315 : CY_UNUSED_PARAMETER(clk_dest);
316 : return Cy_SysClk_PeriphEnableDivider(
317 : IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
318 : #endif
319 : }
320 :
321 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
322 : const struct ifx_cat1_clock *_clock,
323 : uint32_t div)
324 : {
325 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
326 : return Cy_SysClk_PeriPclkSetDivider(
327 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
328 : _clock->channel, div);
329 : #else
330 : CY_UNUSED_PARAMETER(clk_dest);
331 : return Cy_SysClk_PeriphSetDivider(IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
332 : _clock->channel, div);
333 : #endif
334 : }
335 :
336 : static inline cy_rslt_t
337 0 : ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
338 : const struct ifx_cat1_clock *_clock, uint32_t div_int,
339 : uint32_t div_frac)
340 : {
341 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
342 : return Cy_SysClk_PeriPclkSetFracDivider(
343 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
344 : _clock->channel, div_int, div_frac);
345 : #else
346 : CY_UNUSED_PARAMETER(clk_dest);
347 : return Cy_SysClk_PeriphSetFracDivider(
348 : IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int,
349 : div_frac);
350 : #endif
351 : }
352 :
353 0 : static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
354 : const struct ifx_cat1_clock *_clock)
355 : {
356 : #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
357 : return Cy_SysClk_PeriPclkAssignDivider(
358 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
359 : _clock->channel);
360 : #else
361 : return Cy_SysClk_PeriphAssignDivider(
362 : clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
363 : _clock->channel);
364 : #endif
365 : }
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