Line data Source code
1 1 : /*
2 : * Copyright (c) 2025 Microchip Technology Inc.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : /**
8 : * @file mchp_clock_sam_d5x_e5x.h
9 : * @brief Clock control header file for Microchip sam_d5x_e5x family.
10 : *
11 : * This file provides clock driver interface definitions and structures
12 : * for sam_d5x_e5x family
13 : */
14 :
15 : #ifndef INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_
16 : #define INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_
17 :
18 : #include <zephyr/dt-bindings/clock/mchp_sam_d5x_e5x_clock.h>
19 :
20 0 : typedef struct {
21 : /** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
22 1 : bool on_demand_en;
23 :
24 : /** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
25 1 : bool run_in_standby_en;
26 : } clock_mchp_subsys_xosc_config_t;
27 :
28 : /** @brief GCLK generator numbers
29 : * @anchor clock_mchp_gclkgen_t
30 : */
31 0 : typedef enum {
32 : CLOCK_MCHP_GCLKGEN_GEN0,
33 : CLOCK_MCHP_GCLKGEN_GEN1,
34 : CLOCK_MCHP_GCLKGEN_GEN2,
35 : CLOCK_MCHP_GCLKGEN_GEN3,
36 : CLOCK_MCHP_GCLKGEN_GEN4,
37 : CLOCK_MCHP_GCLKGEN_GEN5,
38 : CLOCK_MCHP_GCLKGEN_GEN6,
39 : CLOCK_MCHP_GCLKGEN_GEN7,
40 : CLOCK_MCHP_GCLKGEN_GEN8,
41 : CLOCK_MCHP_GCLKGEN_GEN9,
42 : CLOCK_MCHP_GCLKGEN_GEN10,
43 : CLOCK_MCHP_GCLKGEN_GEN11
44 : } clock_mchp_gclkgen_t;
45 :
46 0 : typedef struct {
47 : /** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
48 1 : bool on_demand_en;
49 :
50 : /** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
51 1 : bool run_in_standby_en;
52 :
53 : /** @brief Enable closed-loop operation */
54 1 : bool closed_loop_en;
55 :
56 : /** @brief Reference source clock selection @see @ref clock_mchp_gclkgen_t */
57 1 : clock_mchp_gclkgen_t src;
58 :
59 : /** @brief Determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input
60 : * frequency (0 - 65535)
61 : */
62 1 : uint32_t multiply_factor;
63 : } clock_mchp_subsys_dfll_config_t;
64 :
65 : /** @brief FDPLL source clocks
66 : * @anchor clock_mchp_fdpll_src_clock_t
67 : */
68 0 : typedef enum {
69 : CLOCK_MCHP_FDPLL_SRC_GCLK0,
70 : CLOCK_MCHP_FDPLL_SRC_GCLK1,
71 : CLOCK_MCHP_FDPLL_SRC_GCLK2,
72 : CLOCK_MCHP_FDPLL_SRC_GCLK3,
73 : CLOCK_MCHP_FDPLL_SRC_GCLK4,
74 : CLOCK_MCHP_FDPLL_SRC_GCLK5,
75 : CLOCK_MCHP_FDPLL_SRC_GCLK6,
76 : CLOCK_MCHP_FDPLL_SRC_GCLK7,
77 : CLOCK_MCHP_FDPLL_SRC_GCLK8,
78 : CLOCK_MCHP_FDPLL_SRC_GCLK9,
79 : CLOCK_MCHP_FDPLL_SRC_GCLK10,
80 : CLOCK_MCHP_FDPLL_SRC_GCLK11,
81 : CLOCK_MCHP_FDPLL_SRC_XOSC32K,
82 : CLOCK_MCHP_FDPLL_SRC_XOSC0,
83 : CLOCK_MCHP_FDPLL_SRC_XOSC1,
84 :
85 : CLOCK_MCHP_FDPLL_SRC_MAX = CLOCK_MCHP_FDPLL_SRC_XOSC1
86 : } clock_mchp_fdpll_src_clock_t;
87 :
88 0 : typedef struct {
89 : /** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
90 1 : bool on_demand_en;
91 :
92 : /** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
93 1 : bool run_in_standby_en;
94 :
95 : /** @brief Reference source clock selection @see @ref clock_mchp_fdpll_src_clock_t */
96 1 : clock_mchp_fdpll_src_clock_t src;
97 :
98 : /** @brief Set the XOSC clock division factor (0 - 2047) */
99 1 : uint32_t xosc_clock_divider;
100 :
101 : /** @brief Set the integer part of the frequency multiplier. (0 - 4095) */
102 1 : uint32_t divider_ratio_int;
103 :
104 : /** @brief Set the fractional part of the frequency multiplier. (0 - 31) */
105 1 : uint32_t divider_ratio_frac;
106 : } clock_mchp_subsys_fdpll_config_t;
107 :
108 : /** @brief RTC source clocks
109 : * @anchor clock_mchp_rtc_src_clock_t
110 : */
111 0 : typedef enum {
112 : CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K,
113 : CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K,
114 : CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K,
115 : CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K
116 : } clock_mchp_rtc_src_clock_t;
117 :
118 0 : typedef struct {
119 : /** @brief RTC source clock selection @see @ref clock_mchp_rtc_src_clock_t */
120 1 : clock_mchp_rtc_src_clock_t src;
121 : } clock_mchp_subsys_rtc_config_t;
122 :
123 0 : typedef struct {
124 : /** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
125 1 : bool on_demand_en;
126 :
127 : /** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
128 1 : bool run_in_standby_en;
129 : } clock_mchp_subsys_osc32k_config_t;
130 :
131 : /** @brief Gclk Generator source clocks
132 : * @anchor clock_mchp_gclk_src_clock_t
133 : */
134 0 : typedef enum {
135 : CLOCK_MCHP_GCLK_SRC_XOSC0,
136 : CLOCK_MCHP_GCLK_SRC_XOSC1,
137 : CLOCK_MCHP_GCLK_SRC_GCLKPIN,
138 : CLOCK_MCHP_GCLK_SRC_GCLKGEN1,
139 : CLOCK_MCHP_GCLK_SRC_OSCULP32K,
140 : CLOCK_MCHP_GCLK_SRC_XOSC32K,
141 : CLOCK_MCHP_GCLK_SRC_DFLL,
142 : CLOCK_MCHP_GCLK_SRC_FDPLL0,
143 : CLOCK_MCHP_GCLK_SRC_FDPLL1,
144 :
145 : CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_FDPLL1
146 : } clock_mchp_gclk_src_clock_t;
147 :
148 0 : typedef struct {
149 : /** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
150 1 : bool run_in_standby_en;
151 :
152 : /** @brief Generator source clock selection @see @ref clock_mchp_gclk_src_clock_t */
153 1 : clock_mchp_gclk_src_clock_t src;
154 :
155 : /** @brief Represent a division value for the corresponding Generator. The actual division
156 : * factor is dependent on the state of div_select (gclk1 0 - 65535, others 0 - 255)
157 : */
158 1 : uint16_t div_factor;
159 : } clock_mchp_subsys_gclkgen_config_t;
160 :
161 0 : typedef struct {
162 : /** @brief gclk generator source of a peripheral clock @see @ref clock_mchp_gclkgen_t*/
163 1 : clock_mchp_gclkgen_t src;
164 : } clock_mchp_subsys_gclkperiph_config_t;
165 :
166 : /** @brief division ratio of mclk prescaler for CPU
167 : * @anchor clock_mchp_mclk_cpu_div_t
168 : */
169 0 : typedef enum {
170 : CLOCK_MCHP_MCLK_CPU_DIV_1 = 1,
171 : CLOCK_MCHP_MCLK_CPU_DIV_2 = 2,
172 : CLOCK_MCHP_MCLK_CPU_DIV_4 = 4,
173 : CLOCK_MCHP_MCLK_CPU_DIV_8 = 8,
174 : CLOCK_MCHP_MCLK_CPU_DIV_16 = 16,
175 : CLOCK_MCHP_MCLK_CPU_DIV_32 = 32,
176 : CLOCK_MCHP_MCLK_CPU_DIV_64 = 64,
177 : CLOCK_MCHP_MCLK_CPU_DIV_128 = 128
178 : } clock_mchp_mclk_cpu_div_t;
179 :
180 : /** @brief MCLK configuration structure
181 : *
182 : * Used for CLOCK_MCHP_SUBSYS_TYPE_MCLKCPU
183 : */
184 1 : typedef struct {
185 : /** @brief division ratio of mclk prescaler for CPU @see @ref clock_mchp_mclk_cpu_div_t */
186 1 : clock_mchp_mclk_cpu_div_t division_factor;
187 : } clock_mchp_subsys_mclkcpu_config_t;
188 :
189 : /** @brief clock rate datatype
190 : *
191 : * Used for setting a clock rate
192 : */
193 1 : typedef uint32_t *clock_mchp_rate_t;
194 :
195 : #endif /* INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_ */
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