Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2016 Open-RnD Sp. z o.o.
       3             :  * Copyright (c) 2016 BayLibre, SAS
       4             :  * Copyright (c) 2017 Linaro Limited.
       5             :  * Copyright (c) 2017 RnDity Sp. z o.o.
       6             :  *
       7             :  * SPDX-License-Identifier: Apache-2.0
       8             :  */
       9             : #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RCAR_CLOCK_CONTROL_H_
      10             : #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RCAR_CLOCK_CONTROL_H_
      11             : 
      12             : #include <zephyr/drivers/clock_control.h>
      13             : #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
      14             : 
      15           0 : struct rcar_cpg_clk {
      16           0 :         uint32_t domain;
      17           0 :         uint32_t module;
      18           0 :         uint32_t rate;
      19             : };
      20             : 
      21             : #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RCAR_CLOCK_CONTROL_H_ */