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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
8 : #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
9 :
10 : #include <zephyr/drivers/clock_control.h>
11 :
12 0 : #define RZ_CGC_SUBCLK_DIV(subclk) \
13 : UTIL_CAT(RZ_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
14 : (DT_PROP(subclk, div))
15 :
16 0 : #define RZ_CGC_SUBCLK_MUL(subclk) \
17 : UTIL_CAT(RZ_CGC_MUL_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
18 : (DT_PROP(subclk, mul))
19 :
20 0 : #define RZ_CGC_DIV_CKIO(n) UTIL_CAT(BSP_CLOCKS_CKIO_ICLK_DIV, n)
21 0 : #define RZ_CGC_MUL_CPU0CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU0_ICLK_MUL, n)
22 0 : #define RZ_CGC_MUL_CPU1CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU1_ICLK_MUL, n)
23 :
24 : #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_ */
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