Line data Source code
1 0 : /*
2 : * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 : * Copyright (c) 2016 BayLibre, SAS
4 : * Copyright (c) 2017-2022 Linaro Limited.
5 : * Copyright (c) 2017 RnDity Sp. z o.o.
6 : * Copyright (c) 2023 STMicroelectronics
7 : *
8 : * SPDX-License-Identifier: Apache-2.0
9 : */
10 : #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11 : #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12 :
13 : #include <zephyr/drivers/clock_control.h>
14 :
15 : #if defined(CONFIG_SOC_SERIES_STM32C0X)
16 : #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
17 : #elif defined(CONFIG_SOC_SERIES_STM32F0X)
18 : #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
19 : #elif defined(CONFIG_SOC_SERIES_STM32F1X)
20 : #if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
21 : #include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
22 : #else
23 : #include <zephyr/dt-bindings/clock/stm32f1_clock.h>
24 : #endif
25 : #elif defined(CONFIG_SOC_SERIES_STM32F3X)
26 : #include <zephyr/dt-bindings/clock/stm32f3_clock.h>
27 : #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
28 : defined(CONFIG_SOC_SERIES_STM32F4X)
29 : #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
30 : #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
31 : #elif defined(CONFIG_SOC_SERIES_STM32F7X)
32 : #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
33 : #elif defined(CONFIG_SOC_SERIES_STM32G0X)
34 : #include <zephyr/dt-bindings/clock/stm32g0_clock.h>
35 : #elif defined(CONFIG_SOC_SERIES_STM32G4X)
36 : #include <zephyr/dt-bindings/clock/stm32g4_clock.h>
37 : #elif defined(CONFIG_SOC_SERIES_STM32L0X)
38 : #include <zephyr/dt-bindings/clock/stm32l0_clock.h>
39 : #elif defined(CONFIG_SOC_SERIES_STM32L1X)
40 : #include <zephyr/dt-bindings/clock/stm32l1_clock.h>
41 : #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
42 : defined(CONFIG_SOC_SERIES_STM32L5X)
43 : #include <zephyr/dt-bindings/clock/stm32l4_clock.h>
44 : #elif defined(CONFIG_SOC_SERIES_STM32MP2X)
45 : #include <zephyr/dt-bindings/clock/stm32mp2_clock.h>
46 : #elif defined(CONFIG_SOC_SERIES_STM32WBX)
47 : #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
48 : #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
49 : #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
50 : #elif defined(CONFIG_SOC_SERIES_STM32WLX)
51 : #include <zephyr/dt-bindings/clock/stm32wl_clock.h>
52 : #elif defined(CONFIG_SOC_SERIES_STM32H5X)
53 : #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
54 : #elif defined(CONFIG_SOC_SERIES_STM32H7X)
55 : #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
56 : #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
57 : #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
58 : #elif defined(CONFIG_SOC_SERIES_STM32MP13X)
59 : #include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
60 : #elif defined(CONFIG_SOC_SERIES_STM32N6X)
61 : #include <zephyr/dt-bindings/clock/stm32n6_clock.h>
62 : #elif defined(CONFIG_SOC_SERIES_STM32U0X)
63 : #include <zephyr/dt-bindings/clock/stm32u0_clock.h>
64 : #elif defined(CONFIG_SOC_SERIES_STM32U3X)
65 : #include <zephyr/dt-bindings/clock/stm32u3_clock.h>
66 : #elif defined(CONFIG_SOC_SERIES_STM32U5X)
67 : #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
68 : #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
69 : #include <zephyr/dt-bindings/clock/stm32wba_clock.h>
70 : #else
71 : #include <zephyr/dt-bindings/clock/stm32_clock.h>
72 : #endif
73 :
74 : /** Common clock control device node for all STM32 chips */
75 1 : #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
76 :
77 : /** RCC node related symbols */
78 :
79 1 : #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
80 0 : #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
81 0 : #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
82 0 : #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
83 0 : #define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
84 0 : #define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
85 0 : #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
86 0 : #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
87 0 : #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
88 0 : #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
89 0 : #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
90 0 : #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
91 :
92 : #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
93 : #define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
94 : #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
95 : #define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
96 : #endif
97 :
98 : #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
99 : #define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
100 : #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
101 : #define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
102 : #else
103 0 : #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
104 : #endif
105 :
106 0 : #define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
107 0 : #define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
108 0 : #define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
109 :
110 0 : #define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre)
111 :
112 : /** STM2H7RS specific RCC dividers */
113 : #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
114 : #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
115 : #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
116 : #define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
117 : #define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
118 : #define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
119 : #define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
120 : #else
121 1 : #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
122 0 : #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
123 0 : #define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
124 0 : #define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
125 0 : #define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
126 0 : #define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
127 : #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
128 :
129 : /** STM2WBA specifics RCC dividers */
130 1 : #define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
131 :
132 0 : #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
133 :
134 : /* To enable use of IS_ENABLED utility macro, these symbols
135 : * should not be defined directly using DT_SAME_NODE.
136 : */
137 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
138 : #define STM32_SYSCLK_SRC_PLL 1
139 : #endif
140 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
141 : #define STM32_SYSCLK_SRC_HSI 1
142 : #endif
143 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
144 : #define STM32_SYSCLK_SRC_HSE 1
145 : #endif
146 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
147 : #define STM32_SYSCLK_SRC_MSI 1
148 : #endif
149 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
150 : #define STM32_SYSCLK_SRC_MSIS 1
151 : #endif
152 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
153 : #define STM32_SYSCLK_SRC_CSI 1
154 : #endif
155 : #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
156 : #define STM32_SYSCLK_SRC_IC2 1
157 : #endif
158 :
159 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
160 : #if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
161 : #if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
162 : #define STM32_CPUCLK_SRC_HSI 1
163 : #elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
164 : #define STM32_CPUCLK_SRC_MSI 1
165 : #elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
166 : #define STM32_CPUCLK_SRC_HSE 1
167 : #elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
168 : #define STM32_CPUCLK_SRC_IC1 1
169 : #endif
170 : #endif /* cpusw clk source is rcc */
171 :
172 : #define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
173 : #endif /* rcc node compatible st_stm32n6_rcc and okay */
174 :
175 : /** PLL node related symbols */
176 :
177 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
178 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
179 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
180 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
181 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
182 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
183 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
184 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
185 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
186 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
187 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
188 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
189 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
190 : #define STM32_PLL_ENABLED 1
191 : #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
192 : #define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
193 : #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
194 : #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
195 : #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
196 : #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
197 : #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
198 : #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
199 : #define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
200 : #define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
201 : #define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
202 : #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
203 : #endif
204 :
205 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
206 : #define STM32_PLLI2S_ENABLED 1
207 : #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
208 : #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
209 : #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
210 : #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
211 : #endif
212 :
213 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
214 : #define STM32_PLLI2S_ENABLED 1
215 : #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
216 : #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
217 : #define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
218 : #define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
219 : #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
220 : #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
221 : #endif
222 :
223 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay)
224 : #define STM32_PLLSAI_ENABLED 1
225 : #define STM32_PLLSAI_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai), div_m)
226 : #define STM32_PLLSAI_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai), mul_n)
227 : #define STM32_PLLSAI_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p)
228 : #define STM32_PLLSAI_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1)
229 : #define STM32_PLLSAI_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q)
230 : #define STM32_PLLSAI_DIVQ_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq)
231 : #if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \
232 : (!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED)
233 : #error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present"
234 : #endif
235 : #define STM32_PLLSAI_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1)
236 : #define STM32_PLLSAI_DIVQ_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1)
237 : #define STM32_PLLSAI_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r)
238 : #define STM32_PLLSAI_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr)
239 : #if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \
240 : (!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED)
241 : #error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present"
242 : #endif
243 : #define STM32_PLLSAI_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1)
244 : #define STM32_PLLSAI_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1)
245 : #endif
246 :
247 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
248 : #define STM32_PLLSAI1_ENABLED 1
249 : #define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m)
250 : #define STM32_PLLSAI1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai1), mul_n)
251 : #define STM32_PLLSAI1_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_p)
252 : #define STM32_PLLSAI1_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_p, 1)
253 : #define STM32_PLLSAI1_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_q)
254 : #define STM32_PLLSAI1_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_q, 1)
255 : #define STM32_PLLSAI1_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_r)
256 : #define STM32_PLLSAI1_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_r, 1)
257 : #endif
258 :
259 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay)
260 : #define STM32_PLLSAI2_ENABLED 1
261 : #define STM32_PLLSAI2_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai2), div_m)
262 : #define STM32_PLLSAI2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai2), mul_n)
263 : #define STM32_PLLSAI2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_p)
264 : #define STM32_PLLSAI2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_p, 1)
265 : #define STM32_PLLSAI2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_q)
266 : #define STM32_PLLSAI2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_q, 1)
267 : #define STM32_PLLSAI2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_r)
268 : #define STM32_PLLSAI2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_r, 1)
269 : #define STM32_PLLSAI2_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_divr)
270 : #define STM32_PLLSAI2_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_divr, 1)
271 : #endif
272 :
273 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
274 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
275 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
276 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
277 : #define STM32_PLL2_ENABLED 1
278 : #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
279 : #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
280 : #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
281 : #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
282 : #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
283 : #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
284 : #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
285 : #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
286 : #define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
287 : #define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
288 : #define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
289 : #define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
290 : #define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
291 : #define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
292 : #endif
293 :
294 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
295 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
296 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
297 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
298 : #define STM32_PLL3_ENABLED 1
299 : #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
300 : #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
301 : #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
302 : #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
303 : #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
304 : #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
305 : #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
306 : #define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
307 : #define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
308 : #define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
309 : #define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
310 : #define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
311 : #endif
312 :
313 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
314 : #define STM32_PLL4_ENABLED 1
315 : #define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
316 : #define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
317 : #define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
318 : #define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
319 : #define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
320 : #define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
321 : #define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
322 : #define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
323 : #define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
324 : #define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
325 : #endif
326 :
327 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
328 : #define STM32_PLL_ENABLED 1
329 : #define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
330 : #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
331 : #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
332 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
333 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
334 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
335 : #define STM32_PLL_ENABLED 1
336 : #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
337 : #define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
338 : #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
339 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
340 : #define STM32_PLL_ENABLED 1
341 : #define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
342 : #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
343 : #endif
344 :
345 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
346 : #define STM32_PLL2_ENABLED 1
347 : #define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
348 : #define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
349 : #endif
350 :
351 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
352 : #define STM32_PLL1_ENABLED 1
353 : #define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
354 : #define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
355 : #define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
356 : #define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
357 : #endif
358 :
359 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
360 : #define STM32_PLL2_ENABLED 1
361 : #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
362 : #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
363 : #define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
364 : #define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
365 : #endif
366 :
367 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
368 : #define STM32_PLL3_ENABLED 1
369 : #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
370 : #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
371 : #define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
372 : #define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
373 : #endif
374 :
375 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
376 : #define STM32_PLL4_ENABLED 1
377 : #define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
378 : #define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
379 : #define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
380 : #define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
381 : #endif
382 :
383 : /** PLL/PLL1 clock source */
384 : #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
385 : DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
386 : #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
387 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
388 : #define STM32_PLL_SRC_MSI 1
389 : #endif
390 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
391 : #define STM32_PLL_SRC_MSIS 1
392 : #endif
393 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
394 : #define STM32_PLL_SRC_HSI 1
395 : #endif
396 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
397 : #define STM32_PLL_SRC_CSI 1
398 : #endif
399 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
400 : #define STM32_PLL_SRC_HSE 1
401 : #endif
402 : #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
403 : #define STM32_PLL_SRC_PLL2 1
404 : #endif
405 :
406 : #endif
407 :
408 : /** PLL2 clock source */
409 : #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
410 : DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
411 : #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
412 : #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
413 : #define STM32_PLL2_SRC_MSI 1
414 : #endif
415 : #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
416 : #define STM32_PLL2_SRC_MSIS 1
417 : #endif
418 : #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
419 : #define STM32_PLL2_SRC_HSI 1
420 : #endif
421 : #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
422 : #define STM32_PLL2_SRC_HSE 1
423 : #endif
424 :
425 : #endif
426 :
427 : /** PLL3 clock source */
428 : #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
429 : DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
430 : #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
431 : #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
432 : #define STM32_PLL3_SRC_MSI 1
433 : #endif
434 : #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
435 : #define STM32_PLL3_SRC_MSIS 1
436 : #endif
437 : #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
438 : #define STM32_PLL3_SRC_HSI 1
439 : #endif
440 : #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
441 : #define STM32_PLL3_SRC_HSE 1
442 : #endif
443 :
444 : #endif
445 :
446 : /** PLL4 clock source */
447 : #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
448 : DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
449 : #define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
450 : #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
451 : #define STM32_PLL4_SRC_MSI 1
452 : #endif
453 : #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
454 : #define STM32_PLL4_SRC_HSI 1
455 : #endif
456 : #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
457 : #define STM32_PLL4_SRC_HSE 1
458 : #endif
459 :
460 : #endif
461 :
462 : /** PLLSAI clock source */
463 : #if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \
464 : DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks)
465 : #define DT_PLLSAI_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai))
466 : #if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
467 : #define STM32_PLLSAI_SRC_HSI 1
468 : #endif
469 : #if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
470 : #define STM32_PLLSAI_SRC_HSE 1
471 : #endif
472 :
473 : #endif
474 :
475 : /** PLLSAI1 clock source */
476 : #if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
477 : DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
478 : #define DT_PLLSAI1_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai1))
479 : #if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
480 : #define STM32_PLLSAI1_SRC_MSI 1
481 : #endif
482 : #if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
483 : #define STM32_PLLSAI1_SRC_HSI 1
484 : #endif
485 : #if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
486 : #define STM32_PLLSAI1_SRC_HSE 1
487 : #endif
488 :
489 : #endif
490 :
491 : /** PLLSAI2 clock source */
492 : #if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai2), okay) && \
493 : DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), clocks)
494 : #define DT_PLLSAI2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai2))
495 : #if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
496 : #define STM32_PLLSAI2_SRC_MSI 1
497 : #endif
498 : #if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
499 : #define STM32_PLLSAI2_SRC_HSI 1
500 : #endif
501 : #if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
502 : #define STM32_PLLSAI2_SRC_HSE 1
503 : #endif
504 :
505 : #endif
506 :
507 : /* On STM32F4 series - PLL and PLLSAI share the same source */
508 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \
509 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
510 : !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
511 : #error "On STM32F4 series, PLL and PLLSAI must have the same source"
512 : #endif
513 :
514 : /* On STM32F7 series - PLL and PLLSAI share the same source */
515 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \
516 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
517 : !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
518 : #error "On STM32F7 series, PLL and PLLSAI must have the same source"
519 : #endif
520 :
521 : /* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
522 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
523 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
524 : !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI1_CLOCKS_CTRL)
525 : #error "On STM32L4 series, PLL / PLLSAI1 must have the same source"
526 : #endif
527 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
528 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
529 : !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
530 : #error "On STM32L4 series, PLL / PLLSAI2 must have the same source"
531 : #endif
532 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
533 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
534 : !DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
535 : #error "On STM32L4 series, PLLSAI1 / PLLSAI2 must have the same source"
536 : #endif
537 :
538 : /** Fixed clocks related symbols */
539 :
540 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
541 : #define STM32_LSE_ENABLED 1
542 : #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
543 : #define STM32_LSE_DRIVING 0
544 : #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
545 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
546 : #define STM32_LSE_ENABLED 1
547 : #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
548 : #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
549 : #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
550 : #else
551 1 : #define STM32_LSE_ENABLED 0
552 0 : #define STM32_LSE_FREQ 0
553 0 : #define STM32_LSE_DRIVING 0
554 0 : #define STM32_LSE_BYPASS 0
555 : #endif
556 :
557 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
558 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
559 : #define STM32_MSI_ENABLED 1
560 : #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
561 : #endif
562 :
563 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
564 : #define STM32_MSI_ENABLED 1
565 : #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
566 : #endif
567 :
568 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
569 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
570 : #define STM32_MSIS_ENABLED 1
571 : #define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
572 : #define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
573 : #else
574 0 : #define STM32_MSIS_ENABLED 0
575 0 : #define STM32_MSIS_RANGE 0
576 0 : #define STM32_MSIS_PLL_MODE 0
577 : #endif
578 :
579 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
580 : DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
581 : #define STM32_MSIK_ENABLED 1
582 : #define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
583 : #define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
584 : #else
585 0 : #define STM32_MSIK_ENABLED 0
586 0 : #define STM32_MSIK_RANGE 0
587 0 : #define STM32_MSIK_PLL_MODE 0
588 : #endif
589 :
590 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
591 : #define STM32_CSI_ENABLED 1
592 : #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
593 : #else
594 0 : #define STM32_CSI_FREQ 0
595 : #endif
596 :
597 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
598 : #define STM32_LSI_ENABLED 1
599 : #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
600 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
601 : #define STM32_LSI_ENABLED 1
602 : #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
603 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
604 : #define STM32_LSI_ENABLED 1
605 : #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
606 : #else
607 0 : #define STM32_LSI_FREQ 0
608 : #endif
609 :
610 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
611 : #define STM32_HSI_DIV_ENABLED 0
612 : #define STM32_HSI_ENABLED 1
613 : #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
614 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
615 : || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \
616 : || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
617 : || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
618 : || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
619 : #define STM32_HSI_DIV_ENABLED 1
620 : #define STM32_HSI_ENABLED 1
621 : #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
622 : #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
623 : #else
624 0 : #define STM32_HSI_DIV_ENABLED 0
625 0 : #define STM32_HSI_DIVISOR 1
626 0 : #define STM32_HSI_FREQ 0
627 : #endif
628 :
629 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
630 : #define STM32_HSE_ENABLED 1
631 : #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
632 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
633 : #define STM32_HSE_ENABLED 1
634 : #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
635 : #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
636 : #define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
637 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
638 : #define STM32_HSE_ENABLED 1
639 : #define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
640 : #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
641 : #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
642 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
643 : #define STM32_HSE_ENABLED 1
644 : #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
645 : #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
646 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
647 : #define STM32_HSE_ENABLED 1
648 : #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
649 : #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
650 : #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
651 : #else
652 0 : #define STM32_HSE_FREQ 0
653 : #endif
654 :
655 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
656 : #define STM32_HSI48_ENABLED 1
657 : #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
658 : #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
659 : #define STM32_HSI48_ENABLED 1
660 : #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
661 : #define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
662 : #endif
663 :
664 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
665 : #define STM32_CKPER_ENABLED 1
666 : #endif
667 :
668 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
669 : #define STM32_CPUSW_ENABLED 1
670 : #endif
671 :
672 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
673 : #define STM32_IC1_ENABLED 1
674 : #define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
675 : #define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
676 : #endif
677 :
678 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
679 : #define STM32_IC2_ENABLED 1
680 : #define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
681 : #define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
682 : #endif
683 :
684 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
685 : #define STM32_IC3_ENABLED 1
686 : #define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
687 : #define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
688 : #endif
689 :
690 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
691 : #define STM32_IC4_ENABLED 1
692 : #define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
693 : #define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
694 : #endif
695 :
696 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
697 : #define STM32_IC5_ENABLED 1
698 : #define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
699 : #define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
700 : #endif
701 :
702 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
703 : #define STM32_IC6_ENABLED 1
704 : #define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
705 : #define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
706 : #endif
707 :
708 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
709 : #define STM32_IC7_ENABLED 1
710 : #define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
711 : #define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
712 : #endif
713 :
714 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
715 : #define STM32_IC8_ENABLED 1
716 : #define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
717 : #define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
718 : #endif
719 :
720 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
721 : #define STM32_IC9_ENABLED 1
722 : #define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
723 : #define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
724 : #endif
725 :
726 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
727 : #define STM32_IC10_ENABLED 1
728 : #define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
729 : #define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
730 : #endif
731 :
732 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
733 : #define STM32_IC11_ENABLED 1
734 : #define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
735 : #define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
736 : #endif
737 :
738 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
739 : #define STM32_IC12_ENABLED 1
740 : #define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
741 : #define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
742 : #endif
743 :
744 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
745 : #define STM32_IC13_ENABLED 1
746 : #define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
747 : #define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
748 : #endif
749 :
750 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
751 : #define STM32_IC14_ENABLED 1
752 : #define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
753 : #define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
754 : #endif
755 :
756 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
757 : #define STM32_IC15_ENABLED 1
758 : #define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
759 : #define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
760 : #endif
761 :
762 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
763 : #define STM32_IC16_ENABLED 1
764 : #define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
765 : #define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
766 : #endif
767 :
768 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
769 : #define STM32_IC17_ENABLED 1
770 : #define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
771 : #define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
772 : #endif
773 :
774 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
775 : #define STM32_IC18_ENABLED 1
776 : #define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
777 : #define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
778 : #endif
779 :
780 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
781 : #define STM32_IC19_ENABLED 1
782 : #define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
783 : #define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
784 : #endif
785 :
786 : #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
787 : #define STM32_IC20_ENABLED 1
788 : #define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
789 : #define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
790 : #endif
791 :
792 : /** Driver structure definition */
793 :
794 1 : struct stm32_pclken {
795 0 : uint32_t bus : STM32_CLOCK_DIV_SHIFT;
796 0 : uint32_t div : (32 - STM32_CLOCK_DIV_SHIFT);
797 0 : uint32_t enr;
798 : };
799 :
800 : /** Device tree clocks helpers */
801 :
802 1 : #define STM32_CLOCK_INFO(clk_index, node_id) \
803 : { \
804 : .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
805 : .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
806 : GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
807 : .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
808 : STM32_CLOCK_DIV_SHIFT, \
809 : }
810 0 : #define STM32_DT_CLOCKS(node_id) \
811 : { \
812 : LISTIFY(DT_NUM_CLOCKS(node_id), \
813 : STM32_CLOCK_INFO, (,), node_id) \
814 : }
815 :
816 0 : #define STM32_DT_INST_CLOCKS(inst) \
817 : STM32_DT_CLOCKS(DT_DRV_INST(inst))
818 :
819 0 : #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
820 0 : #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
821 : (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
822 :
823 0 : #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
824 0 : #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
825 : (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
826 :
827 : /** Clock source binding accessors */
828 :
829 : /**
830 : * @brief Obtain register field from clock source selection configuration.
831 : *
832 : * @param clock clock bit field value.
833 : */
834 1 : #define STM32_DT_CLKSEL_REG_GET(clock) \
835 : (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
836 :
837 : /**
838 : * @brief Obtain position field from clock source selection configuration.
839 : *
840 : * @param clock Clock bit field value.
841 : */
842 1 : #define STM32_DT_CLKSEL_SHIFT_GET(clock) \
843 : (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
844 :
845 : /**
846 : * @brief Obtain mask field from clock source selection configuration.
847 : *
848 : * @param clock Clock bit field value.
849 : */
850 1 : #define STM32_DT_CLKSEL_MASK_GET(clock) \
851 : (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
852 :
853 : /**
854 : * @brief Obtain value field from clock source selection configuration.
855 : *
856 : * @param clock Clock bit field value.
857 : */
858 1 : #define STM32_DT_CLKSEL_VAL_GET(clock) \
859 : (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
860 :
861 : #if defined(STM32_HSE_CSS)
862 : /**
863 : * @brief Called if the HSE clock security system detects a clock fault.
864 : *
865 : * The function is called in interrupt context.
866 : *
867 : * The default (weakly-linked) implementation does nothing and should be
868 : * overridden.
869 : */
870 : void stm32_hse_css_callback(void);
871 : #endif
872 :
873 : #ifdef CONFIG_SOC_SERIES_STM32WB0X
874 : /**
875 : * @internal
876 : * @brief Type definition for LSI frequency update callbacks
877 : */
878 : typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
879 :
880 : /**
881 : * @internal
882 : * @brief Registers a callback to invoke after each runtime measure and
883 : * update of the LSI frequency is completed.
884 : *
885 : * @param cb Callback to invoke
886 : * @return 0 Registration successful
887 : * @return ENOMEM Too many callbacks registered
888 : *
889 : * @note Callbacks are NEVER invoked if runtime LSI measurement is disabled
890 : */
891 : int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
892 : #endif /* CONFIG_SOC_SERIES_STM32WB0X */
893 :
894 : #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
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