Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 Nordic Semiconductor ASA
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_
       8              : #define ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_
       9              : 
      10              : #include <zephyr/drivers/comparator.h>
      11              : 
      12              : #ifdef __cplusplus
      13              : extern "C" {
      14              : #endif
      15              : 
      16            0 : enum comp_mcux_acmp_offset_mode {
      17              :         COMP_MCUX_ACMP_OFFSET_MODE_LEVEL0 = 0,
      18              :         COMP_MCUX_ACMP_OFFSET_MODE_LEVEL1,
      19              : };
      20              : 
      21            0 : enum comp_mcux_acmp_hysteresis_mode {
      22              :         COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL0 = 0,
      23              :         COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL1,
      24              :         COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL2,
      25              :         COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL3,
      26              : };
      27              : 
      28            0 : struct comp_mcux_acmp_mode_config {
      29            0 :         enum comp_mcux_acmp_offset_mode offset_mode;
      30            0 :         enum comp_mcux_acmp_hysteresis_mode hysteresis_mode;
      31            0 :         bool enable_high_speed_mode;
      32            0 :         bool invert_output;
      33            0 :         bool use_unfiltered_output;
      34            0 :         bool enable_pin_output;
      35              : };
      36              : 
      37            0 : enum comp_mcux_acmp_mux_input {
      38              :         COMP_MCUX_ACMP_MUX_INPUT_IN0 = 0,
      39              :         COMP_MCUX_ACMP_MUX_INPUT_IN1,
      40              :         COMP_MCUX_ACMP_MUX_INPUT_IN2,
      41              :         COMP_MCUX_ACMP_MUX_INPUT_IN3,
      42              :         COMP_MCUX_ACMP_MUX_INPUT_IN4,
      43              :         COMP_MCUX_ACMP_MUX_INPUT_IN5,
      44              :         COMP_MCUX_ACMP_MUX_INPUT_IN6,
      45              :         COMP_MCUX_ACMP_MUX_INPUT_IN7,
      46              : };
      47              : 
      48            0 : enum comp_mcux_acmp_port_input {
      49              :         COMP_MCUX_ACMP_PORT_INPUT_DAC = 0,
      50              :         COMP_MCUX_ACMP_PORT_INPUT_MUX,
      51              : };
      52              : 
      53            0 : struct comp_mcux_acmp_input_config {
      54            0 :         enum comp_mcux_acmp_mux_input positive_mux_input;
      55            0 :         enum comp_mcux_acmp_mux_input negative_mux_input;
      56            0 :         enum comp_mcux_acmp_port_input positive_port_input;
      57            0 :         enum comp_mcux_acmp_port_input negative_port_input;
      58              : };
      59              : 
      60            0 : struct comp_mcux_acmp_filter_config {
      61            0 :         bool enable_sample;
      62            0 :         uint8_t filter_count;
      63            0 :         uint8_t filter_period;
      64              : };
      65              : 
      66            0 : enum comp_mcux_acmp_dac_vref_source {
      67              :         COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN1 = 0,
      68              :         COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN2,
      69              : };
      70              : 
      71            0 : struct comp_mcux_acmp_dac_config {
      72            0 :         enum comp_mcux_acmp_dac_vref_source vref_source;
      73            0 :         uint8_t value;
      74            0 :         bool enable_output;
      75            0 :         bool enable_high_speed_mode;
      76              : };
      77              : 
      78            0 : enum comp_mcux_acmp_dm_clock {
      79              :         COMP_MCUX_ACMP_DM_CLOCK_SLOW = 0,
      80              :         COMP_MCUX_ACMP_DM_CLOCK_FAST,
      81              : };
      82              : 
      83            0 : enum comp_mcux_acmp_dm_sample_time {
      84              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T1 = 0,
      85              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T2,
      86              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T4,
      87              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T8,
      88              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T16,
      89              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T32,
      90              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T64,
      91              :         COMP_MCUX_ACMP_DM_SAMPLE_TIME_T256,
      92              : };
      93              : 
      94            0 : enum comp_mcux_acmp_dm_phase_time {
      95              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT0 = 0,
      96              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT1,
      97              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT2,
      98              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT3,
      99              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT4,
     100              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT5,
     101              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT6,
     102              :         COMP_MCUX_ACMP_DM_PHASE_TIME_ALT7,
     103              : };
     104              : 
     105            0 : struct comp_mcux_acmp_dm_config {
     106            0 :         bool enable_positive_channel;
     107            0 :         bool enable_negative_channel;
     108            0 :         bool enable_resistor_divider;
     109            0 :         enum comp_mcux_acmp_dm_clock clock_source;
     110            0 :         enum comp_mcux_acmp_dm_sample_time sample_time;
     111            0 :         enum comp_mcux_acmp_dm_phase_time phase1_time;
     112            0 :         enum comp_mcux_acmp_dm_phase_time phase2_time;
     113              : };
     114              : 
     115            0 : int comp_mcux_acmp_set_mode_config(const struct device *dev,
     116              :                                    const struct comp_mcux_acmp_mode_config *config);
     117              : 
     118            0 : int comp_mcux_acmp_set_input_config(const struct device *dev,
     119              :                                     const struct comp_mcux_acmp_input_config *config);
     120              : 
     121            0 : int comp_mcux_acmp_set_filter_config(const struct device *dev,
     122              :                                      const struct comp_mcux_acmp_filter_config *config);
     123              : 
     124            0 : int comp_mcux_acmp_set_dac_config(const struct device *dev,
     125              :                                   const struct comp_mcux_acmp_dac_config *config);
     126              : 
     127            0 : int comp_mcux_acmp_set_dm_config(const struct device *dev,
     128              :                                  const struct comp_mcux_acmp_dm_config *config);
     129              : 
     130            0 : int comp_mcux_acmp_set_window_mode(const struct device *dev, bool enable);
     131              : 
     132              : #ifdef __cplusplus
     133              : }
     134              : #endif
     135              : 
     136              : #endif /* ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_ */