Line data Source code
1 0 : /*
2 : * Copyright 2023-2024 NXP
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_
8 : #define ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_
9 :
10 0 : #define DMA_MCUX_PXP_CMD_MASK 0xE0
11 0 : #define DMA_MCUX_PXP_CMD_SHIFT 0x5
12 :
13 0 : #define DMA_MCUX_PXP_FMT_MASK 0x1F
14 0 : #define DMA_MCUX_PXP_FMT_SHIFT 0x0
15 :
16 : /*
17 : * In order to configure the PXP for rotation, the user should
18 : * supply a format and command as the DMA slot parameter, like so:
19 : * dma_slot = (DMA_MCUX_PXP_FTM(DMA_MCUX_PXP_FMT_RGB565) |
20 : * DMA_MCUX_PXP_CMD(DMA_MCUX_PXP_CMD_ROTATE_90))
21 : * head block source address: input buffer address
22 : * head block destination address: output buffer address
23 : * source data size: input buffer size in bytes
24 : * source burst length: height of source buffer in pixels
25 : * dest data size: output buffer size in bytes
26 : * dest burst length: height of destination buffer in pixels
27 : */
28 :
29 0 : #define DMA_MCUX_PXP_FMT(x) ((x << DMA_MCUX_PXP_FMT_SHIFT) & DMA_MCUX_PXP_FMT_MASK)
30 0 : #define DMA_MCUX_PXP_CMD(x) ((x << DMA_MCUX_PXP_CMD_SHIFT) & DMA_MCUX_PXP_CMD_MASK)
31 :
32 0 : #define DMA_MCUX_PXP_CMD_ROTATE_0 0
33 0 : #define DMA_MCUX_PXP_CMD_ROTATE_90 1
34 0 : #define DMA_MCUX_PXP_CMD_ROTATE_180 2
35 0 : #define DMA_MCUX_PXP_CMD_ROTATE_270 3
36 :
37 0 : #define DMA_MCUX_PXP_FMT_RGB565 0
38 0 : #define DMA_MCUX_PXP_FMT_RGB888 1
39 0 : #define DMA_MCUX_PXP_FMT_ARGB8888 2
40 :
41 0 : #define DMA_MCUX_PXP_FLIP_MASK 0x3
42 0 : #define DMA_MCUX_PXP_FLIP_SHIFT 0x0
43 :
44 : /*
45 : * In order to configure the PXP to flip, the user should
46 : * supply a flip setting as the DMA linked_channel parameter, like so:
47 : * linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_HORIZONTAL)
48 : */
49 :
50 0 : #define DMA_MCUX_PXP_FLIP(x) ((x << DMA_MCUX_PXP_FLIP_SHIFT) & DMA_MCUX_PXP_FLIP_MASK)
51 :
52 0 : #define DMA_MCUX_PXP_FLIP_DISABLE 0
53 0 : #define DMA_MCUX_PXP_FLIP_HORIZONTAL 1
54 0 : #define DMA_MCUX_PXP_FLIP_VERTICAL 2
55 0 : #define DMA_MCUX_PXP_FLIP_BOTH 3
56 :
57 : #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_ */
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