Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Nuvoton Technology Corporation.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  *
       6              :  */
       7              : 
       8              : #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_NPCX_GDMA_H_
       9              : #define ZEPHYR_INCLUDE_DRIVERS_DMA_NPCX_GDMA_H_
      10              : 
      11            0 : #define NPCX_DMA_ADDR_16B_ALIGN 16U
      12              : 
      13              : /* Macros for DMA channel-config */
      14              : /* config: A 32bit mask specifying the GDMA channel configuration
      15              :  *           - bit 0-5:  Reserved. (default: 0x0)
      16              :  *           - bit 6-7:  Direction  (see dma.h)
      17              :  *                       - 0x0: MEM to MEM
      18              :  *                       - 0x1: MEM to PERIPH
      19              :  *                       - 0x2: PERIPH to MEM
      20              :  *                       - 0x3: reserved for PERIPH to PERIPH
      21              :  *           - bit 8-9:  Transfer Width Select. The address width must be aligned
      22              :  *                       with the selected data width.
      23              :  *                       - 0x0: Byte (8 bits)
      24              :  *                       - 0x1: Word (16 bits)
      25              :  *                       - 0x2: Double-Word (32 bits)
      26              :  *                              This value is required if bit 10 is set to 1.
      27              :  *                       - 0x3: Reserved
      28              :  *           - bit 10:   16-byte transfer (address must be 16-byte aligned)
      29              :  *                       - 0x0: Disable 16-byte transfer
      30              :  *                      - 0x1: Enable 16-byte transfer
      31              :  *           - bit 11:   Destination address direction.
      32              :  *                       - 0x0: Destination address incremented successively. (default)
      33              :  *                       - 0x1: Destination address decremented successively.
      34              :  *           - bit 12:   Source address direction.
      35              :  *                       - 0x0: Source address incremented successively. (default)
      36              :  *                       - 0x1: Source address decremented successively.
      37              :  *           - bit 13:   Destination address fixed.
      38              :  *                       - 0x0: Change the Destination address during the GDMA
      39              :  *                              operation. (default)
      40              :  *                       - 0x1: Fixed address is used for each data transfer from
      41              :  *                              the destination.
      42              :  *           - bit 14:   Source address fixed.
      43              :  *                       - 0x0: Change the source address during the GDMA operation. (default)
      44              :  *                       - 0x1: Fixed address is used for each data transfer from
      45              :  *                              the source.
      46              :  */
      47            0 : #define DMA_NPCX_CONFIG_DIR   FIELD(6, 2)
      48            0 : #define DMA_NPCX_CONFIG_TWS   FIELD(8, 2)
      49            0 : #define DMA_NPCX_CONFIG_BME   10
      50            0 : #define DMA_NPCX_CONFIG_DADIR FIELD(11, 1)
      51            0 : #define DMA_NPCX_CONFIG_SADIR FIELD(12, 1)
      52            0 : #define DMA_NPCX_CONFIG_DAFIX 13
      53            0 : #define DMA_NPCX_CONFIG_SAFIX 14
      54              : 
      55            0 : #define NPCX_GDMA_CHANNEL_CONFIG(inst, name) DT_INST_DMAS_CELL_BY_NAME(inst, name, config)
      56            0 : #define NPCX_GDMA_CONFIG_DIRECTION(config)   GET_FIELD(config, DMA_NPCX_CONFIG_DIR)
      57            0 : #define NPCX_GDMA_CONFIG_BURST_LENGTH(config)                                                      \
      58              :         ((1 << GET_FIELD(config, DMA_NPCX_CONFIG_TWS))                                             \
      59              :          << (IS_BIT_SET(config, DMA_NPCX_CONFIG_BME) ? 0x2 : 0x0))
      60            0 : #define NPCX_GDMA_CONFIG_DSTADDR_ADJ(config)                                                       \
      61              :         (IS_BIT_SET(config, DMA_NPCX_CONFIG_DAFIX)) ? DMA_ADDR_ADJ_NO_CHANGE                       \
      62              :                                                     : GET_FIELD(config, DMA_NPCX_CONFIG_DADIR)
      63            0 : #define NPCX_GDMA_CONFIG_SRCADDR_ADJ(config)                                                       \
      64              :         (IS_BIT_SET(config, DMA_NPCX_CONFIG_SAFIX)) ? DMA_ADDR_ADJ_NO_CHANGE                       \
      65              :                                                     : GET_FIELD(config, DMA_NPCX_CONFIG_SADIR)
      66              : #endif