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1 1 : /*
2 : * Copyright 2025 The ChromiumOS Authors.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : /**
8 : * @file
9 : * @brief Header file for Andes QSPI-NOR XIP flash extended operations.
10 : * @ingroup andes_flash_xip_ex_op
11 : */
12 :
13 : #ifndef __ZEPHYR_INCLUDE_DRIVERS_ANDES_FLASH_XIP_API_EX_H__
14 : #define __ZEPHYR_INCLUDE_DRIVERS_ANDES_FLASH_XIP_API_EX_H__
15 :
16 : /**
17 : * @brief Extended operations for Andes QSPI-NOR XIP flash.
18 : * @defgroup andes_flash_xip_ex_op Andes QSPI-NOR XIP
19 : * @ingroup flash_ex_op
20 : * @{
21 : */
22 :
23 : #ifdef __cplusplus
24 : extern "C" {
25 : #endif
26 :
27 : #include <zephyr/drivers/flash.h>
28 :
29 : /**
30 : * @brief Enumeration for Andes flash extended operations.
31 : */
32 1 : enum flash_andes_xip_ex_ops {
33 : /**
34 : * @brief Get the three status registers (SR1, SR2, SR3).
35 : *
36 : * This operation reads the contents of the three status registers from the flash device.
37 : *
38 : * @param out Pointer to a @ref andes_xip_ex_ops_get_out structure to store the register
39 : * values.
40 : */
41 : FLASH_ANDES_XIP_EX_OP_GET_STATUS_REGS = FLASH_EX_OP_VENDOR_BASE,
42 : /**
43 : * @brief Set the three status registers (SR1, SR2, SR3).
44 : *
45 : * This operation writes new values to the status registers, applying a mask to modify only
46 : * specific bits.
47 : * This operation is protected by a software lock that can be controlled with
48 : * @ref FLASH_ANDES_XIP_EX_OP_LOCK.
49 : *
50 : * @param in Pointer to a @ref andes_xip_ex_ops_set_in structure containing the values and
51 : * masks to write.
52 : */
53 : FLASH_ANDES_XIP_EX_OP_SET_STATUS_REGS,
54 : /**
55 : * @brief Set a software lock to prevent status register modification.
56 : *
57 : * This operation enables or disables a software lock that prevents the
58 : * @ref FLASH_ANDES_XIP_EX_OP_SET_STATUS_REGS operation from executing.
59 : *
60 : * @param in Pointer to a @ref andes_xip_ex_ops_lock_in structure specifying whether to
61 : * enable or disable the lock.
62 : */
63 : FLASH_ANDES_XIP_EX_OP_LOCK,
64 : /**
65 : * @brief Get the current state of the software status register lock.
66 : *
67 : * @param out Pointer to a @ref andes_xip_ex_ops_lock_state_out structure to store the
68 : * current lock state.
69 : */
70 : FLASH_ANDES_XIP_EX_OP_LOCK_STATE,
71 : /**
72 : * @brief Set the SPI command for memory-mapped read mode.
73 : *
74 : * This operation configures the command used by the hardware for Execute-In-Place (XIP) or
75 : * memory-mapped reads.
76 : *
77 : * @param in Pointer to a @ref andes_xip_ex_ops_mem_read_cmd_in structure specifying the
78 : * read command to use.
79 : */
80 : FLASH_ANDES_XIP_EX_OP_MEM_READ_CMD,
81 : };
82 :
83 : /**
84 : * @brief SPI commands for memory-mapped read mode.
85 : *
86 : * These values represent the different SPI read commands that can be configured for memory-mapped
87 : * access using the @ref FLASH_ANDES_XIP_EX_OP_MEM_READ_CMD operation.
88 : * The command codes correspond to standard SPI flash read command opcodes.
89 : */
90 1 : enum flash_andes_xip_mem_rd_cmd {
91 : FLASH_ANDES_XIP_MEM_RD_CMD_03 = 0, /**< Normal Read (0x03) */
92 : FLASH_ANDES_XIP_MEM_RD_CMD_0B = 1, /**< Fast Read (0x0B) */
93 : FLASH_ANDES_XIP_MEM_RD_CMD_3B = 2, /**< Dual I/O Fast Read (0x3B) */
94 : FLASH_ANDES_XIP_MEM_RD_CMD_6B = 3, /**< Quad I/O Fast Read (0x6B) */
95 : FLASH_ANDES_XIP_MEM_RD_CMD_BB = 4, /**< Dual Output Fast Read (0xBB) */
96 : FLASH_ANDES_XIP_MEM_RD_CMD_EB = 5, /**< Quad Output Fast Read (0xEB) */
97 : FLASH_ANDES_XIP_MEM_RD_CMD_13 = 8, /**< Normal Read with 4-byte address (0x13) */
98 : FLASH_ANDES_XIP_MEM_RD_CMD_0C = 9, /**< Fast Read with 4-byte address (0x0C) */
99 : FLASH_ANDES_XIP_MEM_RD_CMD_3C = 10, /**< Dual I/O Fast Read with 4-byte address (0x3C) */
100 : FLASH_ANDES_XIP_MEM_RD_CMD_6C = 11, /**< Quad I/O Fast Read with 4-byte address (0x6C) */
101 : FLASH_ANDES_XIP_MEM_RD_CMD_BC = 12, /**< Dual Output Fast Read with 4-byte address (0xBC) */
102 : FLASH_ANDES_XIP_MEM_RD_CMD_EC = 13, /**< Quad Output Fast Read with 4-byte address (0xEC) */
103 : };
104 :
105 : /**
106 : * @brief Output parameters for @ref FLASH_ANDES_XIP_EX_OP_GET_STATUS_REGS operation.
107 : */
108 1 : struct andes_xip_ex_ops_get_out {
109 : /** Buffer for read status registers. */
110 1 : uint8_t regs[3];
111 : };
112 :
113 : /**
114 : * @brief Input parameters for @ref FLASH_ANDES_XIP_EX_OP_SET_STATUS_REGS operation.
115 : */
116 1 : struct andes_xip_ex_ops_set_in {
117 : /** Status registers to write. */
118 1 : uint8_t regs[3];
119 : /** Mask of status registers to change. */
120 1 : uint8_t masks[3];
121 : };
122 :
123 : /**
124 : * @brief Input parameters for @ref FLASH_ANDES_XIP_EX_OP_LOCK operation.
125 : */
126 1 : struct andes_xip_ex_ops_lock_in {
127 : /** Set to true to enable the lock, false to disable. */
128 1 : bool enable;
129 : };
130 :
131 : /**
132 : * @brief Output parameters for @ref FLASH_ANDES_XIP_EX_OP_LOCK_STATE operation.
133 : */
134 1 : struct andes_xip_ex_ops_lock_state_out {
135 : /** Current lock state. */
136 1 : bool state;
137 : };
138 :
139 : /**
140 : * @brief Input parameters for @ref FLASH_ANDES_XIP_EX_OP_MEM_READ_CMD operation.
141 : */
142 1 : struct andes_xip_ex_ops_mem_read_cmd_in {
143 : /** SPI command used for memory-mapped mode. */
144 1 : enum flash_andes_xip_mem_rd_cmd cmd;
145 : };
146 :
147 : #ifdef __cplusplus
148 : }
149 : #endif
150 :
151 : /**
152 : * @}
153 : */
154 :
155 : #endif /* __ZEPHYR_INCLUDE_DRIVERS_ANDES_FLASH_XIP_API_EX_H__ */
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